Lead Design Engineer

Cadence; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Cadence, a pivotal leader in electronic design, invites experienced verification engineers to join our Bengaluru team. You will work on both existing and new verification environments, aligning with verification experts to meet DV metrics across multiple customer configurations.

The role requires strong Verilog/HVL (SV/e) with UVM, assertions, coverage, and exposure to multi-protocol PHY IPs (SerDes, USB/DPHY, UCIe).

Qualifications

• 5+ years of experience in digital functional verification.
• Experience in multi-protocol PHY IPs (SerDes/USB/DPHY/UCIe).

Responsibilities

• Work with the existing verification environment, add features, or build new environments while ensuring DV metrics across multiple customer configurations.
• Interface with RTL, Physical and Analog design teams and align verification strategy with experts.
• Define, develop and deploy new functional verification methodologies.
• Demonstrate strong fundamentals in verification environment planning, development and test plan creation.
• Proficiency in Verilog, HVL (SV, e) with UVM methodology; experience with assertions, coverage, and constraints.
• RTL and GLS debugging expertise; familiarity with gate-level simulations and formal verification is a plus.

Skills

Functional verification fundamentals

Verification environment planning

Test plan creation

Verilog

HVL/SV/e

UVM methodology

Assertions development

Constraint randomization

Functional coverage

Code coverage

RTL debugging

Education

BE/B.Tech or ME/M.Tech

Tools

Verilog

HVL

UVM

Job description

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Responsibilities

• The role requires working with the existing functional verification environment, addition of new features into the verification environment or creating completely new verification environment from scratch and ensuring various customer configurations are clean meeting required DV metrics. Sometimes there may also be need to support customers in case of any issues with design.
• Participate in Technical alignment with verification expert in Defining verification strategy, architecting verification environment. Also interface with other domains such as RTL , Physical design, Analog design and modelling teams. Technically small team/project depending on the project requriements.
• Contribute towards Defining, developing and deploying new functional verification methodologies.
• The engineers should have strong background in functional verification fundamentals, verification environment planning & development, test plan creation.
• Prior Digital verification experience in some of the serial bus multiprotocol PHY IP’s (such as SerDes, USB/DPHY,UCIe) is expected.
• Other verification domain skills:
• Strong expertise in Verilog, HVL( SV, e) with UVM methodology
• Experience in assertions development/closure, constraint randomization, functional coverage, code coverage.
• Strong RTL and GLS debug skills.
• Expertise in more than two of following skills is desirable and added plus:
• Power-aware RTL set-up, simulation and debug
• Formal verification.
• Gate-level simulations.
• Good to have (not must have): Some experience or understanding and usage of Analog models. Basic awareness of mixed-mode simulations with Analog/digital,-Some exposure to Automotive IP verification (fault injection), emulation exposure though not mandatory but good to have.

Qualification

5+ years experience with B.E/B.Tech or M.E/M.Tech

We’re doing work that matters. Help us solve what others can’t.

Requirements: