Sr Principal Design Engineer

Cadence; Dadri; On-site; INR 2,000,000 - 3,000,000; Full time

Benefits offered by this job

Employee-friendly policies

Opportunities for learning and development

Collaborative work culture

Job summary

Cadence is seeking a Sr Principal Design Engineer to manage a Memory Controller DV group in Noida. This role involves overseeing MDV verification, customer interactions, and mentoring junior engineers while ensuring compliance with quality metrics. Applicants should possess over 11 years of relevant experience in design verification and have expertise in Verilog, SystemVerilog, and UVM methodology.

The ideal candidate will have a strong background in functional verification and previous team leadership experience in areas including DDR and PCIe.

Qualifications

• At least 11+ years of relevant experience including design verification experience.
• Prior experience in leading and managing teams with expertise in DDR, PCIe, UCIe or USB.
• Strong expertise in Verilog, SystemVerilog with UVM methodology.

Responsibilities

• Ensure design aligns with technical and quality metrics.
• Define verification strategy and architect verification environment.
• Lead team interactions with RTL, Subsystem and Performance for design verification.
• Develop and deploy new functional verification methodologies.

Skills

Functional verification fundamentals

Environment planning

Test plan generation

Verilog

SystemVerilog

UVM methodology

AXI

PCIe

UCIe

USB

Education

BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title

Sr Principal Design Engineer

Location

Noida

Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee‑friendly policies focus on the physical and mental well‑being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Summary

The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers. The role requires the ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions. The role will require customer interactions including pre and post‑sales activities, DV methodology review and customer support.

Job Responsibilities

• Ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics.
• Participate in technical alignment with verification experts in defining verification strategy, architecting verification environment.
• Represent DV and technically work/lead team interactions with RTL, Subsystem and Performance for design verification tasks.
• Contribute towards defining, developing, and deploying new functional verification methodologies.
• Participate in interactions with Marketing, AE and Release team when required.
• Review project sign‑off and quality of DDR controller feature verification.

Experience And Technical Skills Required

• At least 11+ years of relevant experience including design verification experience.
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
• Strong expertise in Verilog, SV with UVM methodology.
• AXI and/or CHI experience is highly desirable.
• Prior experience in leading and managing teams with expertise in any of DDR, PCIe, UCIe or USB is strongly required.
• Memory controller verification experience is a plus.

Qualifications

• BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent

Behavioral Skills Required

• Must possess strong written, verbal and presentation skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions.
• Work effectively across functions and geographies.
• Push to raise the bar while always operating with integrity.

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