Sr Principal Design Engineer

Cadence; Pune District; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Cadence is looking for a DFT Engineer with 10-15 years of experience to take ownership of DFT within projects. The role is based in Pune and involves responsibilities such as test architecture definition, implementing RTL changes, and running simulations. Candidates should have experience with high-speed and low-power designs. This is an opportunity to work within a dynamic team and contribute to significant technological advancements.

Qualifications

• 10-15 years experience in DFT and test architecture.
• Experience with RTL changes and simulation debugging.
• Ability to work with high-speed and low power designs.

Responsibilities

• Complete DFT ownership of projects including test architecture definition.
• Identify and implement RTL changes for DFT.
• Perform scan insertion and LEC checks.

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Experience: 10-15 years

Location: Bangalore/Pune

Responsibilities

• Complete DFT ownership of projects including:
• Test architecture definition.
• Identifying and implementing RTL changes for DFT.
• Performing scan insertion, LEC checks, low power CLP checks.
• Developing timing constraints for test mode timing closure.
• Scan and ATPG for different fault models.
• Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
• IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
• Running zero delay and timing simulations and debugging on all the above aspects.
• Supporting post silicon bring up.
• Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
• Experience working on very high speed and low power designs.

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