Staff, VLSI Design Engineering (Verification)

Western Digital; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Western Digital is seeking a Principal Engineer, VLSI Design Engineering to lead verification for complex IP blocks and full-chip designs in Bengaluru. You will drive verification closure, mentor engineers, and collaborate across disciplines to ensure silicon quality and success.

The role emphasizes developing verification environments with UVM, building reusable components, and maintaining SystemVerilog Assertions.

Qualifications

• 8–12 years of relevant experience in VLSI design verification.
• Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering; Masters degree preferred.
• Advanced proficiency in C, Verilog, System Verilog, and UVM.
• Hands-on experience with Xcellium, Verdi, and JasperGold formal verification tools.
• Demonstrated expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off.
• Proven ability to lead technical projects and manage stakeholder relationships effectively.
• Bring in AI/ML/Automation based initiatives.

Responsibilities

• Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs.
• Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks
• Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards
• Drive functional coverage-driven verification closure and ensure comprehensive design validation
• Develop and maintain System Verilog Assertions (SVA) for design verification, including coding, porting, and maintenance activities
• Collaborate with design architects, RTL designers, and post-silicon validation teams to ensure seamless verification integration
• Create and optimize verification automation tools and scripts to enhance design and verification productivity
• Investigate, debug, and perform root-cause analysis of design failures through cross-functional team collaboration
• Mentor junior engineers and contribute to the continuous improvement of verification methodologies and best practices

Skills

C

Verilog

SystemVerilog

UVM

Education

Bachelor's degree in Electronics and Communication Engineering (ECE) / VLSI / Electrical Engineering

Masters degree preferred

Tools

Xcellium

Verdi

JasperGold

Job description

We are seeking an experienced Principal Engineer, VLSI Design Engineering to lead verification efforts for complex IP blocks and fullchip designs. In this role, you will drive functional verification closure, mentor engineering teams, and collaborate across multiple disciplines to ensure design quality and silicon success.

Key Responsibilities:

• Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs
• Design and implement verification environments using industry-standard UVM (Universal Verification Methodology) frameworks
• Develop reusable and scalable verification components, including bus functional models, monitors, checkers, and scoreboards
• Drive functional coverage-driven verification closure and ensure comprehensive design validation
• Develop and maintain System Verilog Assertions (SVA) for design verification, including coding, porting, and maintenance activities
• Collaborate with design architects, RTL designers, and post-silicon validation teams to ensure seamless verification integration
• Create and optimize verification automation tools and scripts to enhance design and verification productivity
• Investigate, debug, and perform root-cause analysis of design failures through cross-functional team collaboration
• Mentor junior engineers and contribute to the continuous improvement of verification methodologies and best practices

Qualifications:

Required Qualifications:

• 8 to 12 years of relevant experience in VLSI design verification
• Bachelors degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering; Masters degree preferred
• Advanced proficiency in C, Verilog, System Verilog, and UVM (Universal Verification Methodology)
• Hands-on experience with industry-standard verification tools including Xcellium, Verdi, and JasperGold formal verification tools
• Demonstrated expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off
• Proven ability to lead technical projects and manage stakeholder relationships effectively
• Bring in AI/ML/Automation based initiatives
• Willingness to learn new tools and related methodologies
• Excellent written and verbal communication skills with demonstrated ability to adapt to dynamic project requirements and deliver results under challenging schedules

Preferred Qualifications:

• Experience with NAND flash memory protocols and memory design verification
• Track record of mentoring junior engineers and contributing to process improvements
• Experience with formal verification methodologies and assertion-based verification