Principal Design Engineer

Cadence; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Cadence in Bengaluru seeks an experienced Design Verification Engineer to verify interconnect IP and subsystems. You will craft verification plans, build reusable testbenches, and drive coverage closure in a cross-functional DV team.

Expect 8+ years of DV experience, strong SystemVerilog/UVM skills, automated flows, and scripting with Perl or shell. This role is on-site in Bengaluru, collaborating with DV, architecture, design and firmware teams.

Qualifications

• BS in EE/Computer Engineering or equivalent required.
• 8+ years of design verification experience.
• Strong knowledge of interconnects, NoCs and DV fundamentals.
• SystemVerilog, UVM experience for testbench development.
• Experience with automated verification flows.
• Scripting with Perl or Unix shell desirable.

Responsibilities

• Design Verification for interconnect IP.
• Craft and execute verification plans for complex designs.
• Responsible for coverage collection and closure.
• Collaborate with DV/Arch/Design/FW teams to identify coverage scope.

Skills

Design verification

Interconnects & NoCs

SystemVerilog

UVM

Testbenches

Scripting (Perl/Unix shell)

Automation of test flows

Education

Bachelor's degree in EE/Computer Engineering

Job description

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

• Design Verification for interconnect IP
• Relevant experience in interconnect and subsystems is strongly preferred
• Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
• Responsible for coverage collection and closure
• Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Required Skills And Experience

• 8+ years of design verification experience
• BS (or higher) in EE/Computer Engineering
• Strong technical and interpersonal skills
• Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
• Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches
• Experience with development of fully automated flows
• Exposure to scripting languages like Perl, Unix shell or similar languages
• Experience with Formal Verification will be a plus
• Experience with Gate Level Simulations
• Excellent written and oral communication skills necessary

We’re doing work that matters. Help us solve what others can’t.

Requirements: