Principal Design Engineer

Cadence; Pune District; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Cadence is seeking an experienced Design Verification Engineer in Pune to lead projects from concept to verification closure. The ideal candidate will have a strong background in functional verification and proven skills in UVM and SystemVerilog.

Applicants should possess a BE/BTech/ME/MTech in Electrical/Electronics/VLSI and have over 7 years of experience in design verification. Previous experience in IP verification of memory IP (DDR/HBM/GDDR) is an advantage.

Qualifications

• 7+ years of Design Verification experience with SV/UVM.
• Strong background in functional verification fundamentals.
• Experience in environment planning, test plan generation, and environment development.

Responsibilities

• Verify complex designs and lead projects from concept to verification closure.
• Develop functional verification environments.

Skills

Design Verification

UVM

SystemVerilog

Functional Verification

Education

BE/BTech/ME/MTech in Electrical / Electronics / VLSI

Job description

Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• BE/BTech/ME/MTech - Electrical / Electronics / VLSI with experience as a design and verification engineer.
• 7+ years of Design Verification experience with SV/UVM.
• Strong background on functional verification fundamentals, environment planning, test plan generation, and environment development.
• Design Verification experience verifying complex designs and leading projects from concept to verification closure.
• Strong hands-on UVM and SystemVerilog coding experience and functional verification environment development.

Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.

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