RTL Design Leads/Architect | 9-12yrs

Capgemini Engineering; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Capgemini Engineering in PAN India seeks a senior VLSI design engineer to drive architecture to tape-out. You will define microarchitecture, code RTL, and collaborate with Synthesis, STA, PD, and DFT teams to meet performance, power, and area goals.

The role requires 8+ years in VLSI, strong Verilog/SystemVerilog or VHDL, and scripting skills. You will work on complex units and contribute to design flows with a focus on backend integration.

Qualifications

• 8+ years of experience in VLSI design.
• Strong Verilog/SystemVerilog or VHDL skills.
• Experience in defining microarchitecture and design of complex design units.
• Proficient in advanced design practices (Lint, CDC, and Low Power Design).
• Familiar with CPU instruction sets (ARM, RISC-V, or x86).
• Proficient with scripting (Perl, Python, C).
• Good communication and interpersonal skills.

Responsibilities

• Own feasibility studies for defining the system architecture, requirements, and external interfaces.
• Develop microarchitecture and logic design in collaboration with functional leads to deliver design from architecture to tape-out.
• Perform RTL coding, Lint checks, CDC tests, and creating timing constraint files.
• Work closely with Synthesis, STA, PD, and DFT teams to meet functional requirements, performance, power, and area goals.
• Develop flows and tools as necessary in support of design activities.

Skills

Verilog/SystemVerilog

VHDL

RTL coding

Microarchitecture

Synthesis/STA tools

Low Power Design

Scripting (Perl, Python, C)

ARM/RISC-V/x86 ISA

Communication skills

Education

BSc in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Synthesis tools

STA tools

Job description

• Own feasibility studies for defining the system architecture, requirements, and external interfaces;
• Develop microarchitecture and logic design in collaboration with functional leads to deliver design from architecture to tape-out;
• Perform RTL coding, Lint checks, CDC tests, and creating timing constraint files;
• Work closely with Synthesis, STA, PD, and DFT teams to meet all functional requirements performance, power, and area goals;
• Develop flows and tools as necessary in support of design activities.

Your profile:

• Work location: PAN India
• NP: Max 45days
• 8+ year experience in VLSI design
• BSC/MSC in Electrical/Computer engineering;
• Strong Verilog/System Verilog or VHDL skills;
• Experience in defining microarchitecture and design of complex design units;
• Proficient in advanced design practices (Lint, CDC, and Low Power Design);
• Proficient with the various backend tools (synthesis and STA);
• Familiar with CPU (ARM, RISC-V, or x86) instruction set;
• Proficiency using Perl/C/Python scripting and programming;
• Good communication and interpersonal skills.