Engineer II, Layout Design

SiTime; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

SiTime in Bengaluru is seeking a Layout Design Engineer II to lead block-level chip planning and perform custom analog layout design for CMOS and BiCMOS circuits. You will coordinate with offshore designers, train juniors, and help establish standard layouts and processes across sites.

The role requires 5+ years in layout for analog and full-custom blocks, proficiency with Cadence Virtuoso, and a deep understanding of parasitics and device matching.

Qualifications

• BA/BS degree in Layout Design or related field or equivalent experience.
• 5+ years of experience in layout design for analog and full-custom digital blocks.
• Experience with TSMC 180nm, 65nm, 22nm process technologies.
• Proficiency with Cadence Virtuoso and DRC/LVS/ERC debugging tools (PVS or Calibre).
• Strong understanding of parasitics, matching, crosstalk, and layout-dependent effects.
• Ability to automate workflows with scripts; willingness to mentor juniors.
• Must be able to lift up to 5 lbs.

Responsibilities

• Collaborate remotely with global design and layout teams across centers and time zones.
• Lead and perform custom analog layout design at block and sub-block levels for CMOS/BiCMOS.
• Execute schematic-driven layout design adhering to constraints.
• Create area-efficient block layouts meeting circuit design requirements.
• Develop block floorplans, power distribution networks, shielding, and matching layouts.
• Verify layouts and ensure DRC, LVS, and ERC signoff.
• Contribute to chip-level routing and layout-related activities.
• Support chip integration, verification, and tape-out activities.
• Train and mentor junior layout engineers and offshore contractors.

Skills

Layout design

Analog & digital blocks

Team collaboration

Education

BA/BS in Layout Design or related field

Tools

Cadence Virtuoso

Mentor Calibre

PVS / DRC/LVS debugging

Job description

About SiTime
SiTime is the Precision Timing company.
Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.
Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .
Job Summary
The Layout Design Engineer II will lead block-level chip planning and perform custom Analog Layout Design for CMOS and BiCMOS circuits. This role includes reviewing and coordinating work performed by offshore layout designers, training junior layout engineers and offshore contractors, contributing to the development of standard layout methodologies across sites, and helping establish processes and procedures that ensure high-quality layout design
Responsibilities

• Collaborate remotely with local and global design and layout teams across multiple design centers and time zones
• Lead and perform custom analog layout design at the functional block, block, sub-block, leaf cell, and standard cell levels for CMOS and BiCMOS circuits
• Execute schematic-driven layout design while adhering to design constraints
• Create area-efficient functional block layouts that meet circuit design requirements
• Develop block-level floor plans, power distribution networks, shielding structures, and device-matching layouts
• Verify layouts and ensure successful DRC, LVS, and ERC signoff
• Contribute to chip-level routing and other layout-related activities
• Support chip integration, verification, and tape-out activities
• Provide support for additional projects as required by management
• Train and mentor junior layout engineers and offshore layout contractors
• Contribute to the development of common best practices and workflows across all sites
• Help establish and improve processes and procedures to achieve high layout quality
  

Qualifications & Requirements

• BA/BS degree in Layout Design or a related field, or equivalent experience
• 5+ years of experience in layout design for analog and full-custom digital blocks
• Experience with TSMC 180nm, 65nm, 22nm process technologies
• Proficiency with layout editing tools in the Cadence Virtuoso design environment
• Solid working knowledge of DRC, LVS, and ERC debugging using Cadence PVS or Mentor Calibre
• Understanding of layout concepts, including parasitics, matching, crosstalk, layout-dependent effects, latch-up, IR drop, electromigration (EM), and deep N-well and NTN isolation
• Strong ability to solve device matching, electromigration, signal integrity, and power distribution challenges while meeting area constraints
• Knowledge with chip-level floorplanning and analog block integration
• Knowldge with chip-level integration, verification, and tape-out
• Ability to use productivity-enhancing tools and design scripts to automate and improve workflow efficiency
• Must be able to lift, push, and pull up to 5 lbs
  

Desired Characteristics & Attributes

• Strong attention to detail; organized, accurate, and able to develop efficient layout techniques
• Proven track record of delivering work on time
• Self-motivated team player with strong communication skills
• Ability to work effectively in a fast-paced, collaborative team environment
  

Compensation Range
At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.
In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.
Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

• Innovation on Top – Philosophies of Innovation with Rajesh Vashist
• Fabrication Knowledge – An Interview with Rajesh Vashist
• SiTime Corporation – YouTube