Sr Engineer STA

UST; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

UST in Bengaluru seeks an experienced Timing Closure and Validation engineer with 5-8 years in synthesis/constraints development and timing closure. You will own subsystem STA closure and provide feedback to the PnR owner, with hands-on PrimeTime work and strong timing debugging skills.

Experience on 7nm/5nm and below and proficiency in scripting (TCL, Perl) are essential. Independent work ethic and ability to drive sign-off activities are required.

Qualifications

• 5-8 years of minimum experience in synthesis/constraints development and validation.
• Ownership of subsystem STA closure and feedback to PnR owner.
• Hands-on PrimeTime experience is a must.
• Good debugging experience on timing issues and able to debug independently.
• Understanding of timing constraints and timing-related debugging skills.
• Experience with lower tech nodes like 7nm, 5nm and below.
• Understanding of scripting languages like TCL, Perl.

Skills

Synthesis

Constraints Development

Constraints Validation

Timing Closure

Timing Sign-off

PrimeTime

Timing debugging

7nm

5nm

Tcl scripting

Perl scripting

Tools

PrimeTime

Tcl

Perl

Job description

• Around 5-8 years of minimum exp in Synthesis/Constraints Development and Validation/Timing Closure and Sign-off ( blocks/fullchip)
• Complete Ownership of Subsystem level STA closure, Includes giving feedback to PnR owner
• Hands on experience with PrimeTime is must.
• Good debugging experience on Timing issues and debug the same independently
• Understanding of timing constraints and constraints related debugging skills
• Should have worked on lower tech nodes like 7nm , 5nm and below.
• Understanding of scripting language like tcl, perl etc is added.