STA/Synthesis Engineer - Chennai

N Human Resources & Management Systems; Chennai District; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

N Human Resources & Management Systems is seeking an experienced STA/Synthesis engineer to drive timing closure and methodology across complex SoCs. You will lead signoff activities and collaborate with RTL and Physical Design teams.

The role requires hands-on STA/Synthesis experience, strong TCL scripting, and Unix proficiency, with mentoring responsibilities for a small team.

Qualifications

• 4+ years of hands-on STA and Synthesis experience.
• Strong TCL scripting and Unix environment skills.
• Solid knowledge of timing signoff flows and constraint development.

Responsibilities

• Logic-aware synthesis, LEC, and VCLP signoff
• SDC and UPF constraint development, including DFT-aware constraints
• Pre- and post-layout timing closure across corners and modes
• Manual ECO generation to resolve timing and DRC violations
• Timing closure at block, subsystem and full-chip level
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• Partner with RTL design and Physical Design teams on SoC timing closure

Skills

STA & Synthesis

TCL scripting

Unix environment

Timing signoff

Job description

Key Responsibilities:

- Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff

- SDC and UPF constraint development, including DFT-aware constraints

- Pre- and post-layout timing closure across corners and modes

- Manual ECO generation to resolve timing and DRC violations

- Timing closure at block, subsystem and full-chip level

- Lead and mentor a team of 4-5 engineers on STA/Synthesis practices

- Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements:

- 4+ years of hands‑on experience in STA and Synthesis

- Strong TCL scripting and Unix environment skills

- Comprehensive knowledge of timing signoff flows and constraint development