Staff Engineer – STA & Synthesis

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru seeks a technically strong Staff Engineer with hands-on STA and RTL-to-gate synthesis for complex ASIC/SoC designs. The role centers on timing closure, synthesis optimization, constraint development, and PPA improvement across advanced nodes.

You will drive RTL synthesis and timing analysis, develop SDC constraints, perform setup/hold analysis across MMMC corners, and collaborate with RTL, Physical Design, DFT, and architecture teams to ensure sign-off

Qualifications

• 7-12 years hands-on experience in STA and RTL synthesis for ASIC/SoC designs.
• Strong expertise in Synopsys PrimeTime and Design Compiler or equivalent industry-standard tools.
• Proficiency in SDC constraints, timing exceptions, clock definitions, and constraint debugging.
• Experience MMMC analysis, timing derates, OCV/AOCV/POCV, and PVT corner analysis.
• Strong knowledge of synthesis optimization, timing-driven mapping, and PPA trade-offs.
• Experience analyzing timing reports and driving root-cause resolution.
• Proficiency in Tcl scripting and automation using Python or Perl.

Responsibilities

• Drive RTL synthesis, timing analysis, and optimization for complex IP and SoC designs.
• Develop, validate, and maintain timing constraints using SDC, including clocks, generated clocks, exceptions, and I/O delays.
• Perform setup/hold analysis, timing path analysis, and root-cause debugging across PVT corners and operating modes.
• Optimize synthesis results for timing, power, and area (PPA).
• Analyze and resolve timing violations involving logic depth, fanout, transition, capacitance, and interconnect effects.
• Execute multi-mode, multi-corner (MMMC) STA and support timing closure across implementation stages.
• Collaborate with RTL, Physical Design, DFT, and architecture teams to resolve timing and synthesis challenges.
• Perform equivalence checks and ensure consistency between RTL and synthesized netlists.
• Drive sign-off readiness through timing reports, constraint validation, and systematic violation closure.

Skills

STA

RTL synthesis

Synopsys PrimeTime

Design Compiler

SDC constraints

Clock definitions

MMM C analysis

Tcl scripting

Python/Perl

PPA optimization

Education

B.E./B.Tech/M.E./M.Tech in Electrical Eng/ Electronics or related

Tools

Synopsys PrimeTime

Design Compiler

Tcl

Python

Perl

Job description

We are looking for a technically strong Staff Engineer with hands-on expertise in Static Timing Analysis (STA) and RTL-to-gate synthesis for complex ASIC/SoC designs. The role focuses on timing closure, synthesis optimization, constraint development, and PPA improvement across advanced technology nodes.

Key Responsibilities

• Drive RTL synthesis, timing analysis, and optimization for complex IP and SoC designs.
• Develop, validate, and maintain timing constraints using SDC, including clocks, generated clocks, exceptions, and I/O delays.
• Perform setup/hold analysis, timing path analysis, and root-cause debugging across PVT corners and operating modes.
• Optimize synthesis results for timing, power, and area (PPA).
• Analyze and resolve timing violations involving logic depth, fanout, transition, capacitance, and interconnect effects.
• Execute multi-mode, multi-corner (MMMC) STA and support timing closure across implementation stages.
• Collaborate with RTL, Physical Design, DFT, and architecture teams to resolve timing and synthesis challenges.
• Perform equivalence checks and ensure consistency between RTL and synthesized netlists.
• Drive sign-off readiness through timing reports, constraint validation, and systematic violation closure.

Required Technical Skills

• 7-12 years of hands-on experience in STA and RTL synthesis for ASIC/SoC designs.
• Strong expertise in Synopsys PrimeTime and Design Compiler or equivalent industry-standard tools.
• Proficiency in SDC constraints, timing exceptions, clock definitions, and constraint debugging.
• Strong understanding of setup/hold timing, clock uncertainty, skew, latency, and signal integrity effects.
• Experience with MMMC analysis, timing derates, OCV/AOCV/POCV, and PVT corner analysis.
• Strong knowledge of synthesis optimization, timing-driven mapping, and PPA trade-offs.
• Experience analyzing timing reports and driving root-cause resolution.
• Proficiency in Tcl scripting and automation using Python or Perl.

Preferred Qualifications

• Experience with advanced technology nodes and high-performance SoC designs.
• Exposure to physical-aware synthesis, post-route timing correlation, and sign-off STA.
• Understanding of low-power design techniques and DFT-related timing considerations.

Education: B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics, or a related discipline.