STA Engineer

HrdWyr; Bengaluru Urban; Sur place; INR 2 500 000 - 4 500 000; Plein temps

Résumé du poste

HrdWyr is seeking an experienced SOC timing engineer to drive chip-level STA convergence from early stages through signoff. The role involves top-level floor planning, clock planning, and defining timing constraints across modes including DFT.

Required 5–8 years in SOC timing convergence, with strong timing concepts and experience in low power design across multiple power domains. Proficiency in TCL, Perl, or Python for automation is essential.

Qualifications

• 5 to 8 years of SOC timing convergence experience.
• Synthesis and equivalence check experience.
• Strong timing concepts.
• Experience with low power design involving multiple power domains.
• Proficiency in scripting languages such as TCL, Perl, or Python for automation.
• Familiarity with industry-standard EDA tools for STA like Tempus and PrimeTime
• Exposure to complex design having multiple asynchronous clocks.

Responsabilités

• Responsible for chip level STA convergence from early stages to signoff.
• Participate in top level floor plan and clock planning.
• IP & SoC timing constraints definition for all modes including DFT
• Multimode-multi corner timing analysis.
• Block and SoC level timing convergence.
• Block and SoC level Synthesis.
• Block and SoC level equivalence check.

Connaissances

SOC timing convergence

Timing concepts

Asynchronous clocks

Low power design

TCL scripting

Python scripting

Perl scripting

Synthesis

Equivalence check

Outils

Tempus

PrimeTime

Description du poste

• Responsible for chip level STA convergence from early stages to signoff.
• Participate in top level floor plan and clock planning.
• IP & SoC timing constraints definition for all modes including DFT
• Multimode-multi corner timing analysis.
• Block and SoC level timing convergence.
• Block and SoC level Synthesis.
• Block and SoC level equivalence check.

Experience Required:

• 5 to 8 years of experience in SOC level timing convergence
• Synthesis and equivalence check
• Strong timing concepts
• Working knowledge of low power design involving multiple power domains.
• Proficiency in scripting languages such as TCL, Perl, or Python for automation.
• Familiarity with industry-standard EDA tools for STA like Tempus and PrimeTime
• Exposure to complex design having multiple asynchronous clocks.