Static Timing Analysis (STA) Lead

Tech Mahindra Limited; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Tech Mahindra in Bengaluru is seeking an experienced STA Lead with deep expertise in ASIC timing analysis and timing closure across block and full-chip designs. The role requires hands-on use of industry-standard EDA tools and strong understanding of STA methodologies, ECO flows, and signoff checks.

You will drive timing closure across synthesis, PnR, and signoff, analyze setup/hold violations, work with cross-functional teams, review STA reports, and contribute to automation via TCL scripting

Qualifications

• 7+ years of STA and timing closure experience.
• Bachelor’s or Master’s degree in Electronics, Electrical, or VLSI Engineering.
• Hands-on experience with STA tools such as ICC2, Innovus, and Fusion Compiler.
• Proficiency in TCL scripting for automation.

Responsibilities

• Develop, analyze, and validate timing constraints (SDC) including clocks, generated clocks, IO constraints, and exceptions.
• Drive timing closure across synthesis, PnR, and signoff stages.
• Analyze and resolve setup, hold, transition, capacitance, crosstalk, and logical DRC violations.
• Work with Physical Design, Synthesis, and Clocking teams to fix timing issues using ECO techniques.
• Perform signoff STA across multiple PVT corners and modes (functional, scan, low-power, test).
• Review STA reports and provide actionable recommendations for design optimization.
• Support ECO implementation and verification to meet timing and QoR targets.
• Contribute to methodology improvements and automation using scripting (TCL/Perl/Shell).

Skills

STA & timing closure

Timing constraints (SDC)

ECO flows

Signoff checks

Scripting (TCL/Shell)

Education

Electronics / Electrical / VLSI Engineering degree

Tools

ICC2

Innovus

Fusion Compiler

Job description

We are seeking an experienced STA Lead with strong expertise in ASIC timing analysis and timing closure across block and/or full‑chip designs. The role requires deep understanding of STA methodologies, constraints, ECO flows, and signoff checks, along with hands‑on experience using industry‑standard EDA tools on advanced technology nodes.

Key Responsibilities

• Develop, analyze, and validate timing constraints (SDC) including clocks, generated clocks, IO constraints, and exceptions
• Drive timing closure across synthesis, PnR, and signoff stages
• Analyze and resolve setup, hold, transition, capacitance, crosstalk, and logical DRC violations
• Work closely with Physical Design, Synthesis, and Clocking teams to fix timing issues using ECO techniques
• Perform signoff STA across multiple PVT corners and modes (functional, scan, low‑power, test)
• Review STA reports and provide actionable recommendations for design optimization
• Support ECO implementation and verification to meet timing and QoR targets
• Contribute to methodology improvements and automation using scripting (TCL / Perl / Shell)

Required Qualifications

• 7+ years of relevant experience in STA and timing closure roles
• Bachelor’s or Master’s degree in Electronics / Electrical / VLSI Engineering or related field
• Strong fundamentals of ASIC design flow and timing concepts
• Hands‑on experience with STA tools such as:

Understanding of ICC2 / Innovus / Fusion Compiler timing interfaces

• Good understanding of PnR impact on timing (CTS, routing, ECOs)
• Proficiency in TCL scripting for STA automation and analysis