STA/Synthesis Engineer

7Rays Semiconductors; Bengaluru; On-site; INR 2,400,000 - 4,000,000; Full time

Job summary

7Rays Semiconductors in Bengaluru seeks a seasoned Synthesis and STA engineer to drive timing closure for SoC projects. You will lead a small team, mentor juniors, and work across RTL design, PD, and HM teams to ensure robust timing closure from prelayout to tapeout.

Responsibilities include performing Synthesis and STA, handling UPF/DFT constraints, generating timing reports, and creating ECOs to fix violations while coordinating with cross-functional teams in India.

Qualifications

• Hands-on experience with synthesis and STA in complex SoC flows.
• Experience with FE inputs, LEC environment, UPF cleanup, and VCLP signoff.
• Knowledge of SDC constraints, DFT SDC, GCA, and timing convergence.
• Hands-on RTL-to-GDS timing closure across prelayout/postlayout.
• Ability to write manual ECOs to fix timing violations and DRCs.
• Strong TCL scripting and UNIX environment skills.
• Leadership of a 4–5 member team with mentoring on STA/Synthesis.
• Coordinate with RTL, PD and HM teams for SoC timing closure.

Responsibilities

• Lead STA/Synthesis tasks and drive timing closure for SoC.
• Prepare prelayout and postlayout timing reports for placement, CTS, and clock gating checks.
• Create ECOs to fix timing violations and DRCs.
• Collaborate with RTL, PD, and HM teams to ensure robust timing closure across blocks.

Skills

Synthesis

Static Timing Analysis

UPF/DFT constraints

TCL scripting

UNIX environment

ECOs for timing fixes

RTL design collaboration

Timing closure

DFT SDC constraints

Team leadership

Job description

• Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
• Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff.
• USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing convergence, Timing Signoff, Merging Modes
• Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
• Knowledge on the Timing closure on Sub system level & Block level and Chip level.
• Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
• Good Knowledge of TCL scripting and UNIX env.
• Leading the team 4 to 5 team members by guiding and mentoring on the STA /Synthesis.
• Prelayout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs and final tapaout timing closure skills across corners and modes Must work RTL design team, PD team and HMs team for overall timing closure for SoC