Technical Lead I - VLSI STA SD

UST; Bengaluru; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

UST Bengaluru seeks an experienced STA/ Synthesis engineer with 5-8 years of minimum experience in Synthesis, Constraints Development and Validation, Timing Closure and Sign-off for blocks and full-chip. Own subsystem level STA closure, provide feedback to PnR owner, hands-on PrimeTime, and strong timing debugging skills.

Candidates should understand timing constraints, debugging techniques, and have exposure to 7nm and 5nm nodes; scripting in Tcl and Perl is a plus.

Qualifications

• 5-8 years of minimum experience in Synthesis/Constraints Development and Validation/Timing Closure and Sign-off (blocks/fullchip).
• Ownership of Subsystem level STA closure with feedback to PnR owner.
• Hands-on experience with PrimeTime is a must.
• Good debugging experience on timing issues and the ability to debug independently.
• Understanding of timing constraints and related debugging skills.
• Experience with lower tech nodes like 7nm, 5nm and below.
• Understanding of scripting languages like Tcl and Perl.
• Team player.

Responsibilities

• Own subsystem level STA closure and provide feedback to PnR owner.
• Hands-on PrimeTime debugging for timing issues.
• Explain timing constraints and debugging techniques.
• Work with lower tech nodes (7nm, 5nm and below).
• Apply TCL/Perl scripting to debug and automate flows.

Skills

Perl

Physical Design

Static Timing Analysis

Synopsys PrimeTime

Tools

Tcl

Perl scripting

Job description

Role Description

Around 5-8 years of minimum exp in Synthesis/Constraints Development and Validation/Timing Closure and Sign-off ( blocks/fullchip) Complete Ownership of Subsystem level STA closure, Includes giving feedback to PnR owner Hands on experience with PrimeTime is must. Good debugging experience on Timing issues and debug the same independently Understanding of timing constraints and constraints related debugging skills Should have worked on lower tech nodes like 7nm , 5nm and below. Understanding of scripting language like tcl, perl etc is added. Should be good Team player.

Role Description

Around 5-8 years of minimum exp in Synthesis/Constraints Development and Validation/Timing Closure and Sign-off ( blocks/fullchip) Complete Ownership of Subsystem level STA closure, Includes giving feedback to PnR owner Hands on experience with PrimeTime is must. Good debugging experience on Timing issues and debug the same independently Understanding of timing constraints and constraints related debugging skills Should have worked on lower tech nodes like 7nm , 5nm and below. Understanding of scripting language like tcl, perl etc is added. Should be good Team player.

Skills

Perl, Physical Design, Static Timing Analysis, Synopsys PrimeTime