Static Timing Analysis Engineer

Ciliconchip Circuit; Bengaluru Urban; On-site; INR 1,200,000 - 1,900,000; Full time

Job summary

A leading semiconductor design firm in India is seeking a qualified Specialist in STA and timing closure. The ideal candidate should hold a Bachelor’s or Master’s degree in Electrical Engineering or Electronics & Communications, with 1 to 5 years of experience in timing closure. Key responsibilities include developing timing constraints, working with architects, and validating design constraints. Strong scripting skills in TCL, Python, or Perl are essential, alongside excellent analytical and problem-solving abilities. The firm offers an opportunity to work on cutting-edge semiconductor technologies and processes.

Qualifications

• 1 to 5 years of experience in STA, timing closure work.
• Hands-on experience in ASIC timing constraints generation.
• Deep understanding of various functional and test modes.
• Strong scripting skills (TCL, Python, or Perl) for design automation.
• Good communication and collaboration across cross-functional teams.

Responsibilities

• Understand design architecture and timing requirements.
• Develop timing constraints and validate.
• Work with architects to generate block and full chip timing constraints.
• Analyze timing from synthesis to verify constraints.
• Generate block and full-chip timing constraints with architects and logic designers.
• Assess scenarios and margin strategies with Synthesis & Design teams.
• Work on SDC for block/partition/full-chip including IO budgeting and constraint merging.
• Coordinate with third-party IP to derive timing signoff requirements.

Skills

STA and timing closure

Scripting skills (TCL, Python, Perl)

Problem-solving and analytical skills

Communication and interpersonal skills

Education

Bachelor’s or Master’s degree in Electrical Engineering or Electronics & Communications

Tools

Timevision

Fishtail

Genus

Prime Time

Tempus

Tweaker

Job description

Responsibilities

• Understand Design Architecture and timing requirements
• Develop timing constraints – SDC and validate
• Work with Physical design to close SDC related timing issues.
• Analysis of timing from synthesis to verify constraints.
• Work with architects and logic designers to generate block and full chip timing constraints.
• Analyse scenarios and margin strategies with Synthesis & Design team.
• Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints.
• Work with third party IP, derive timing signoff requirements.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or Electronics & Communications with 1 to 5 years of experience in STA, timing closure related work.
• Hands‑on experience in ASIC timing constraints generation and timing closure.
• Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST.
• Deep understanding and experience in various functional and test modes.
• Good fundamental on Physical design implementation.
• Knowledge on CLP, low power design is desirable
• Validate timing constraints for Block and Partitions.
• Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.
• Excellent problem‑solving and analytical skills, with a track record of delivering high‑quality designs on schedule.
• Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment.
• Ability to work cross‑functionally with various teams and be productive under aggressive schedules.
• Proven ability to lead and mentor junior engineers, fostering their professional growth and development.

Preferred Qualifications

• Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology.
• Has at least worked on full chip STA closure of large size silicon.
• Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development.
• Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration.