STA Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru seeks an experienced Static Timing Analysis Engineer to define timing constraints and drive full-chip timing closure across modes and corners.

You will collaborate with Physical Design, DFT, and Front-End teams to validate functional and timing modes, and you will develop SDC constraints while guiding timing-driven fixes and ECO automation.

Qualifications

• 5+ years specializing in STA and timing closure for complex SoCs.
• Expertise in MCMM STA and SI/crosstalk analysis.
• Deep understanding of CDC and SDC constraint writing.
• Advanced TCL scripting for timing reporting and ECO automation.

Responsibilities

• Define timing constraints, lead full-chip timing closure across modes and corners.
• Run MCMM STA, analyze setup/hold, max transition, max capacitance, and SI issues.
• Guide timing-driven placement and routing fixes with Physical Design teams.
• Perform timing ECO generation (auto and manual) and verify closure.
• Collaborate with DFT and Front-End teams on timing modes.

Education

B.E. / B.Tech / M.E. / M.Tech in Microelectronics, Electrical Engineering, ECE, or VLSI Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

As a Static Timing Analysis (STA) Engineer, you will be responsible for defining timing constraints, leading full-chip timing closure, and ensuring signoff readiness across all operating modes and corners.

Education Requirements

• Degree: B.E. / B.Tech / M.E. / M.Tech in Microelectronics, Electrical Engineering, ECE, or VLSI Engineering.

Key Responsibilities

• Develop, validate, and maintain block-level and chip-level SDC timing constraints.
• Run multi-corner multi-mode (MCMM) STA and analyze setup, hold, max transition, max capacitance, and crosstalk (SI) violations.
• Work closely with Physical Design engineers to guide timing-driven placement and routing fixes.
• Perform timing ECO generation (both automated and manual) and verify timing closure.
• Collaborate with DFT and Front-End teams to validate functional, scan, and BIST timing modes.

Technical Qualifications

• Experience: 5+ years specializing in STA and timing closure for complex SoCs.
• Tools: Expertise in Synopsys PrimeTime or Cadence Tempus.
• Nodes: Experience with advanced node effects (PBA vs. MBA, POCV/AOCV, signal integrity, electromigration).
• Skills: Deep comprehension of clock domain crossing (CDC), complex SDC constraint writing, and physical timing closure methodologies.
• Scripting: Advanced TCL scripting capabilities for custom timing reporting and ECO automation.