LPDDR IP Design Engineer

Synopsys Inc; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Synopsys Inc. seeks a Sr. Staff ASIC Digital Design Engineer to lead DDR LPDDR PHY IP development.

You will contribute across design phases from specification to productization, writing Verilog/SystemVerilog and coordinating with verification, timing, DFT, and power teams to ensure robust, high-performance IP. The role emphasizes driving design automation and improving flows, with a focus on memory PHY architectures and collaborating with a global, diverse team to shape the next generation of

Qualifications

• BS in Electrical Engineering (or equivalent).
• 6+ years of experience in complex technical development.
• Strong Verilog/SystemVerilog design and coding skills.
• Experience with linting, synthesis, timing, DFT, and power optimization.

Responsibilities

• Lead and contribute across all DDR LPDDR PHY IP design phases from spec to productization.
• Write and review Verilog/SystemVerilog code for LPDDR PHY IP.
• Coordinate with Verification, Timing, DFT, and Power teams on analyses and fixes.
• Maintain and improve design automation flows.

Skills

Verilog/SystemVerilog

Front-end design flow

Communication

Memory PHY knowledge

Education

BS in Electrical Engineering

Job description

Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.

LPDDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products. All current and next-generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.

We are looking for Sr. Staff ASIC Digital Design Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution. Be part of a global diverse team that pushes boundaries on LPDDR PHY IP development and solution, your passion and expertise will shape the next generation of product innovation, performance, and efficiency.

Job Description

In this role, you will be in a leadership role to contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.

• Designing and micro-architecting LPDDR PHY IP writing Verilog and SystemVerilog code and design specification
• Conduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members
• Analyzing and fixing Lint, CDC/RDC, DFT, Timing, and power issues
• Maintain and improve design automating flow and process

Required Skills

• BS in Electrical Engineering and a minimum of 6 years of experience in complex technical development
• Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation
• Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
• Exhibit excellent communication skills and be self-motivated
• Understanding of memory and memory PHY architecture is a plus