Senior /Staff AMS Layout engineer-DPG-LPDDR

Micron Technology; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Micron Technology is seeking a Senior/Staff AMS Layout engineer to own the LPDDR PHY layout, addressing signal integrity, symmetry, and JEDEC compliance. You will guide analog/mixed-signal blocks, steer layout-aware co-design with circuits, and drive post-layout fixes with automation and AI‑driven techniques.

The role requires deep expertise in high-speed LPDDR interfaces, layout replication, power distribution, and signoff protection.

Qualifications

• 3–12 years of hands-on analog and high-speed layout experience.
• Experience with LPDDR interfaces and layout symmetry for multi‑lane blocks.
• Strong knowledge of DRC/LVS, parasitic extraction, and silicon‑accurate layouts.
• Scripting experience to automate layout tasks and data-driven optimization.

Responsibilities

• Own and drive custom analog and mixed-signal LPDDR layout for PHY blocks.
• Lead high‑speed LPDDR interface layout execution and SI challenges.
• Architect scalable layout strategies for DQ/DQS lanes while ensuring symmetry.
• Collaborate with circuit, verification, and silicon teams to close timing and noise issues.
• Drive post‑layout optimization, ECOs, and JEDEC‑compliant designs.

Skills

Analog layout

High-speed layout

LPDDR interfaces

Scripting (Python/TCL)

AI/ML concepts

Automation & flows

Parasitic extraction / DRC/LVS

Power integrity

Tools

SKILL

Python

TCL

Job description

Senior /Staff AMS Layout engineer-DPG-LPDDR

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

• Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, including Datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy
• 3-12 years of solid hands‑on experience in custom analog and high‑speed layout design, with proven expertise in implementing and delivering critical analog blocks and LPDDR/high-speed interfaces at advanced technology nodes
• Lead high-speed LPDDR (LPDDRx) interface layout execution, solving complex signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes
• Architect and implement scalable array-based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and multi-channel scalability
• Drive integration of custom digital and mixed‑signal blocks within the PHY (training logic, calibration engines, test/debug circuitry), ensuring optimal clocking, congestion management, and isolation from sensitive analog regions
• Lead layout‑aware co‑design with circuit teams, enabling early closure of timing, noise, IR, EM, and parasitic effects, and influencing design decisions from a layout perspective
• Establish robust power distribution, grounding, and isolation strategies, including guard rings, deep N‑well usage, decoupling, and domain separation for high‑speed and analog‑sensitive regions
• Own physical verification and signoff closure:
  • DRC/LVS, parasitic extraction, and simulation correlation
  • Ensure silicon‑accurate performance for analog‑intensive and high‑speed LPDDR blocks
• Drive post‑layout optimization and ECOs, resolving margin, yield, and manufacturability challenges while ensuring JEDEC compliance
• Collaborate cross‑functionally with architecture, circuit, verification, and silicon debug teams to enable first‑pass silicon success and high‑volume manufacturability
• Own and drive PPA optimization, delivering measurable improvements in power efficiency, area utilization, and performance
• Mentor engineers and contribute to layout methodologies and best practices, including VXL‑compatible flows, design reviews, and continuous improvement initiatives
• Leveraging Artificial Intelligence
• Leverage automation and advanced techniques:
  • Apply scripting (SKILL/Python/TCL) to improve productivity
  • Use AI/ML concepts as a value‑add for data‑driven optimization and layout automation

Job Profile(s):

Semiconductor Design Engineer 4

Relocation level: (TBD)

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.