Senior VLSI RTL Design Engineer

HCL Technologies Limited; Bengaluru; On-site; INR 2,000,000 - 3,500,000; Full time

Job summary

HCL Technologies Limited in Bengaluru, India, is hiring a Senior RTL Design Engineer to develop and integrate RTL IPs with strong quality checks and signoff. The role focuses on designing, validating, and ensuring seamless SoC readiness through AMBA interfaces and industry-standard protocols.

The candidate should have 4–15+ years of experience in RTL IP development, with proficiency in Verilog/SystemVerilog and scripting, and a background in Python or similar languages for automation.

Qualifications

• Proficiency in RTL design using Verilog/SystemVerilog.
• Experience with AMBA interfaces (AXI/APB/AHB) and peripheral protocols.
• Strong debugging, analysis and scripting skills.

Responsibilities

• Develop synthesizable RTL (Verilog/SystemVerilog) for IP blocks and subsystems.
• Integrate IPs into subsystem/SoC hierarchies ensuring correct clock, reset, power, and interfaces.
• Conduct RTL quality checks and signoff (Lint/CDC/RDC) prior to backend handoff.

Skills

RTL design

Verilog/SystemVerilog

Python scripting

Cross-functional collaboration

Education

B.Tech / M.Tech in Electronics / Electrical / Computer Engineering

Tools

SpyGlass Lint

CDC

RDC

Job description

We are Hiring: Senior VLSI RTL Design Engineer.

Min 4 to 15+ Years of Experience.

Job Summary:

We are looking for an RTL IP-Level Design Engineer responsible for designing, integrating, and ensuring the quality of RTL IPs through comprehensive static and functional quality checks. The role involves ownership of RTL from development through quality signoff prior to backend handoff.

Key Responsibilities

RTL Design & IP Development:

• Develop synthesizable RTL (Verilog / SystemVerilog) for IP blocks and subsystems based on micro-architecture specifications.
• Implement clean, scalable, and reusable IP RTL following coding guidelines and industry best practices.
• Design and maintain wrappers, parameterized RTL, and configuration logic.

IP Integration & SoC Readiness

• Integrate IPs into subsystem / SoC-level hierarchies.
• Ensure correct clock, reset, power, and interface connectivity.
• Support AMBA-based interfaces (AXI/APB/AHB) and peripheral protocols (SPI, I2C, UART).

RTL Quality Checks & Signoff – Lint /CDC / RDC analysis

Required Skills & Qualifications:

Technical Skills:

• RTL Quality Tools: SpyGlass Lint / CDC / RDC.

Programming/Scripting:

• Proficiency in Python/Perl/Shell scripting for automation.

Education:

• B.Tech / M.Tech in Electronics / Electrical / Computer Engineering or equivalent.

Soft Skills:

• Strong analytical and debugging skills.
• Good communication and cross-functional collaboration.