RTL Design Engineer

HCL Technologies Limited; Bengaluru; On-site; INR 1,500,000 - 2,400,000; Full time

Benefits offered by this job

Competitive compensation and benefits

Job summary

HCL Technologies Limited in Bengaluru is seeking an RTL Design Engineer with 5-11 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation. You will work with design, verification and synthesis teams to ensure RTL is implemented correctly and meets timing and integration requirements.

The role offers exposure to cutting-edge ASIC/SoC technologies, a fast-paced environment, and strong learning and career growth

Qualifications

• Strong experience in RTL design using Verilog/SystemVerilog or VHDL
• Hands-on experience in ASIC/SoC development
• Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs
• Experience in functional verification and RTL debugging
• Knowledge of timing analysis, timing closure, and SDC constraints
• Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle
• Exposure to UVM-based verification environments
• Experience with Python, Perl, or Shell scripting
• Familiarity with STA and synthesis flows
• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field

Skills

RTL design

SystemVerilog

Verilog

VHDL

ASIC/SoC dev

Functional verification

Timing analysis

Education

Bachelor's or Master's in EE/EC/CS

Tools

UVM-based verification

Python scripting

Shell scripting

Job description

RTL Design Engineer | 5-12 Years We are seeking an RTL Design Engineer with 5-11 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.

Key Requirements:

• Strong experience in RTL design using Verilog/SystemVerilog or VHDL
• Hands-on experience in ASIC/SoC development
• Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs
• Experience in functional verification and RTL debugging
• Knowledge of timing analysis, timing closure, and SDC constraints
• Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle

Good to Have:

• Exposure to UVM-based verification environments
• Experience with Python, Perl, or Shell scripting
• Familiarity with STA and synthesis flows

Qualification:

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field

Why Join Us?

• Opportunity to work on cutting-edge ASIC/SoC technologies
• Collaborative and fast-paced engineering environment
• Strong learning and career growth opportunities
• Competitive compensation and benefits package