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HCLTech is seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.
This role emphasizes RTL design using Verilog/SystemVerilog or VHDL, functional verification, timing analysis, and collaboration across Design, Verification, and Synthesis teams throughout the development cycle.
We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.