Senior RTL Design Engineer

Edveon Technologies Pvt Ltd; Chennai District; On-site; INR 3,000,000 - 6,000,000; Full time

Benefits offered by this job

Competitive salary

Benefits package

Job summary

Edveon Technologies Pvt Ltd in Chennai seeks an experienced RTL Design Engineer with hands-on Verilog/SystemVerilog to develop and implement RTL for complex ASIC/SoC designs, including synthesis, timing closure, and tape-out.

You will design synthesizable RTL, translate specifications into robust RTL, work with verification and physical teams, resolve synthesis and timing issues, and contribute to timing constraints and design reviews.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field.
• 5+ years of hands-on RTL Design experience for ASIC/SoC projects.
• Strong expertise in Verilog/SystemVerilog and synthesizable RTL coding.
• Strong understanding of digital design, FSMs, datapaths, timing, and microarchitecture.

Responsibilities

• Design and develop synthesizable RTL for digital blocks, IPs, and subsystems using Verilog/SystemVerilog.
• Translate specifications and microarchitecture into efficient and robust RTL.
• Work with verification teams to support functional verification and debug design issues.
• Analyze and resolve synthesis, lint, CDC, and timing issues.
• Define and review SDC constraints and support timing closure.
• Integrate RTL blocks into larger subsystems and ensure functional correctness.
• Follow RTL coding standards and contribute to design reviews and quality improvements.
• Collaborate with architecture, verification, synthesis, and physical design teams through the development cycle.

Skills

Verilog/SystemVerilog

RTL design

digital design

FSMs

timing

microarchitecture

Education

Bachelor's/Master's degree in Electrical/Electronics Engineering or related field

Tools

Xcelium

VCS

SpyGlass

JasperGold

VC Formal

Job description

We are looking for an experienced RTL Design Engineer with strong hands-on expertise in Verilog/SystemVerilog to develop and implement RTL for complex ASIC/SoC designs. The ideal candidate should have a strong understanding of digital design and experience taking designs through synthesis, timing closure, and tape-out

Key Responsibilities:

• Design and develop synthesizable RTL for digital blocks, IPs, and subsystems using Verilog/SystemVerilog.
• Translate specifications and microarchitecture into efficient and robust RTL.
• Work with verification teams to support functional verification and debug design issues.
• Analyze and resolve synthesis, lint, CDC, and timing issues.
• Define and review SDC constraints and support timing closure.
• Integrate RTL blocks into larger subsystems and ensure functional correctness.
• Follow RTL coding standards and contribute to design reviews and quality improvements.
• Collaborate with architecture, verification, synthesis, and physical design teams through the development cycle.

Required Qualifications:

• Bachelor's/Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field.
• 5+ years of hands-on RTL Design experience for ASIC/SoC projects.
• Strong expertise in Verilog/SystemVerilog and synthesizable RTL coding.
• Strong understanding of digital design, FSMs, datapaths, timing, and microarchitecture.
• Proficiency with tools such as Xcelium, VCS, SpyGlass, JasperGold (JG), and VC Formal (VCF).

Why Join us?

• Opportunity to work on cutting-edge chip designs for innovative products.
• Work with a dynamic and skilled team of engineers.
• Competitive salary and benefits package.
• Career growth opportunities in a fast-evolving field.

1/3A 3B, Siruseri Natham Link Road,
Siruseri, Chennai, Tamil Nadu, 600130

USA Edveon Inc

440 N Wolfe Rd, Cube E040
Sunnyvale, CA 94085