RTL Design Engineer Role

HCL Technologies Limited; Bengaluru; On-site; INR 2,000,000 - 4,000,000; Full time

Job summary

HCL Technologies Limited is seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive high-performance digital designs from architecture to implementation. You will work with Design, Verification, and Synthesis teams to ensure robust RTL and effective debugging.

The role requires strong RTL design skills in Verilog/SystemVerilog or VHDL, hands-on ASIC/SoC development, and expertise in timing analysis and SDC constraints.

Qualifications

• Bachelor's or Master's in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• 5-12 years of ASIC/SoC design experience.
• Strong RTL design using Verilog/SystemVerilog or VHDL.
• Hands-on ASIC/SoC development and verification experience.
• Familiar with timing analysis, SDC constraints, lint/CDC.
• Ability to collaborate with Design, Verification, and Synthesis teams.

Responsibilities

• Develop high-performance digital designs from architecture to implementation.
• Contribute to functional verification and RTL debugging.
• Collaborate with Design, Verification, and Synthesis teams throughout the development cycle.
• Assist in timing closure and constraint satisfaction throughout the project lifecycle.

Skills

RTL design

Verilog/SystemVerilog

VHDL

ASIC/SoC

Digital design

Functional verification

RTL debugging

Timing analysis

Timing closure

SDC constraints

Lint/CDC

Cross-team collaboration

Education

Bachelor's or Master's in EE/ Electronics/ CE

Tools

Python

Perl

Shell scripting

Job description

We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.

Key Requirements:

• Strong experience in RTL design using Verilog/SystemVerilog or VHDL
• Hands-on experience in ASIC/SoC development
• Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs
• Experience in functional verification and RTL debugging
• Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.
• Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle

Good to Have:

• Exposure to UVM-based verification environments
• Experience with Python, Perl, or Shell scripting
• Familiarity with STA and synthesis flows

Qualification:

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field

Why Join Us?

• Opportunity to work on cutting-edge ASIC/SoC technologies
• Collaborative and fast-paced engineering environment
• Strong learning and career growth opportunities
• Competitive compensation and benefits package