VLSI - RTL/ASIC&SOC frontend Design

HCLTech; Bengaluru; Hybrid; INR 1,200,000 - 2,000,000; Full time

Benefits offered by this job

Competitive salary and benefits package

Opportunity for professional development

Collaborative and dynamic work environment

Job summary

HCLTech is seeking a highly motivated RTL Design Engineer with 7-15 years of experience to join our growing team in Bengaluru, India. This position involves designing and developing complex digital logic for next-generation integrated circuits.

The ideal candidate will have expertise in RTL design methodologies and verification, with opportunities to work on leading-edge technologies and challenging projects within a collaborative work environment.

Competitive salary and benefits are offered.

Qualifications

• 7-10 years of solid experience in RTL design for ASICs or SoCs.
• In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines).
• Proven ability to design and verify high-performance and efficient digital circuits.

Responsibilities

• Design and develop RTL code for digital logic blocks and modules using Verilog or VHDL.
• Perform comprehensive functional verification using industry-standard methodologies (e.g., UVM).
• Conduct static timing analysis (STA) and participate in timing closure activities.

Skills

RTL design methodologies

Verilog

VHDL

Functional verification

Static timing analysis

Digital design principles

Problem-solving skills

Collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree (a plus)

Tools

ModelSim

Cadence Incisive

Synopsys VCS

Job description

We are seeking a highly motivated RTL Design Engineer with 7-15 years of experience to join our growing team. You will play a vital role in the design and development of complex digital logic for next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in RTL design methodologies and verification.

Experience: 6 to 14Years

Mode: Hybrid

Email:[e-mail]

Responsibilities

• Design and develop RTL code for digital logic blocks and modules using Verilog or VHDL
• Perform comprehensive functional verification using industry-standard methodologies (e.g., UVM)
• Conduct static timing analysis (STA) and participate in timing closure activities
• Integrate designed modules into larger subsystems and ensure seamless functionality
• Collaborate effectively with design, verification, and synthesis teams throughout the development cycle
• Write clear, concise, and well-documented RTL code adhering to coding standards
• Stay current with advancements in RTL design tools and methodologies

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
• 7-10 years of solid experience in RTL design for ASICs or SoCs
• In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
• Proven ability to design and verify high-performance and efficient digital circuits
• Expertise in Verilog or VHDL with a strong understanding of coding styles and best practices
• Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS)
• Familiarity with SDC (Standard Delay Constraint) format for timing analysis
• Excellent problem-solving skills and a meticulous attention to detail
• Strong communication and collaboration skills to work effectively in a team environment
• Competitive salary and benefits package
• Opportunity to work on leading-edge technologies and projects
• Collaborative and dynamic work environment
• Potential for professional development and career advancement

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