Application Specific Integrated Circuit Design Engineer

Globex Digital; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Globex Digital Corp. seeks a Senior ASIC Engineer with 4+ years of hands-on RTL design experience focused on SOC integration and IP development. You will work with Verilog/SystemVerilog, ensuring RTL quality through lint and CDC checks, and apply AMBA protocol knowledge across AXI/AHB/APB.

Knowledge of timing and power concepts is a plus. You will collaborate with physical design, verification, DFT and software teams to debug issues and review design documents for multiple subsystems,

Qualifications

• Senior ASIC Engineer with IP RTL design for SOC environments.
• Expertise in RTL quality checks including lint and CDC.
• Experience with AMBA bus protocols and related interfaces.
• Knowledge of scripting languages and EDA tools for design flows.

Responsibilities

• Collaborate across design, verification, DFT and SW teams.
• Set up, run and debug RTL integration across subsystems.
• Review design documents for multiple subsystems.
• Support timing, power, and protocol compliance in SOC IP flows.

Skills

RTL design

RTL coding

RTL integration

RTL quality checks

SOC/IP design

AMBA protocols

Bus protocols (AXI/AHB/APB)

Scripting (Make, Perl, Python)

EDA tools (Spyglass, Synopsys DC)

Tools

Spyglass Lint/CDC

Synopsys DC

Job description

Mandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)

Experience : 4+ Years

Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols)

Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

In depth knowledge on RTL quality checks (Lint, CDC)

Knowledge of synthesis and low power is a plus

Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

Good understanding of timing concepts

Knowledge of one or more of the interface protocols

• b. DDR
• c. Ethernet
• d. I2C, UART, SPI

Expertise in setting up and using tools like

• a. Spyglass Lint/CDC
• b. Synopsys DC

Understanding of scripting languages like Make flow, Perl ,shell, python etc

Understanding of processor architecture and/or ARM debug architecture is a plus

Able to help and debug issues for multiple subsystems

Able to create/review design documents for multiple subsystems

Able to support physical design, verification, DFT and SW teams on design queries and reviews