RTL Design Engineer

HCLTech; Hyderabad; On-site; INR 1,500,000 - 3,000,000; Full time

Benefits offered by this job

Competitive salary and benefits package

Opportunity to work on leading-edge technologies

Potential for professional development

Job summary

A technology solutions provider in Hyderabad is seeking a highly motivated RTL Design Engineer with 7-12 years of experience. You will design complex digital logic for integrated circuits and perform verification tasks. The ideal candidate has strong expertise in RTL design using Verilog or VHDL and will work in a collaborative environment. This full-time position offers competitive salary and benefits, as well as professional growth opportunities.

Qualifications

• 7-12 years of solid experience in RTL design for ASICs or SoCs.
• In-depth knowledge of digital design principles.
• Expertise in Verilog or VHDL with strong understanding of coding styles.

Responsibilities

• Design and develop RTL code for digital logic blocks using Verilog or VHDL.
• Perform comprehensive functional verification using industry-standard methodologies.
• Conduct static timing analysis and participate in timing closure activities.

Skills

RTL design methodologies

Verilog

VHDL

Functional verification

Timing analysis

Communication skills

Problem-solving

Education

Bachelor's degree in Electrical Engineering

Master's degree

Tools

ModelSim

Cadence Incisive

Synopsys VCS

Job description

Overview

We HCL are seeking a highly motivated RTL Design Engineer with 7-12 years of experience to join our growing team. You will play a vital role in the design and development of complex digital logic for next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in RTL design methodologies and verification.

Responsibilities

• Design and develop RTL code for digital logic blocks and modules using Verilog or VHDL
• Perform comprehensive functional verification using industry-standard methodologies (e.g., UVM)
• Conduct static timing analysis (STA) and participate in timing closure activities
• Integrate designed modules into larger subsystems and ensure seamless functionality
• Collaborate effectively with design, verification, and synthesis teams throughout the development cycle
• Write clear, concise, and well-documented RTL code adhering to coding standards
• Stay current with advancements in RTL design tools and methodologies

Qualifications

• Bachelor\'s degree in Electrical Engineering, Computer Engineering, or a related field (Master\'s degree a plus)
• 7-12 years of solid experience in RTL design for ASICs or SoCs
• In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
• Proven ability to design and verify high-performance and efficient digital circuits
• Expertise in Verilog or VHDL with a strong understanding of coding styles and best practices
• Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS)
• Familiarity with SDC (Standard Delay Constraint) format for timing analysis
• Excellent problem-solving skills and meticulous attention to detail
• Strong communication and collaboration skills to work effectively in a team environment
• Competitive salary and benefits package
• Opportunity to work on leading-edge technologies and projects
• Collaborative and dynamic work environment
• Potential for professional development and career advancement

Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Other
• Industries: Manufacturing and IT Services and IT Consulting