Senior Static Timing Analysis Engineer

Larsen & Toubro Ltd; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Larsen & Toubro Ltd in Bengaluru seeks a Senior Principal Engineer - STA to oversee full chip/subsystem STA convergence from early stages to signoff. You will work with logic design and DFT teams to define and implement constraints for multiple work modes, and participate in floorplanning and clock planning.

Candidate should have strong experience in ASIC timing constraints, Primetime/PT-DMSA, IO timing budgeting, and TCL/Python scripting.

Qualifications

• Strong experience in ASIC timing constraints generation, validation and timing closure.
• Expertise in Primetime and timing eco using PT-DMSA - full chip and block level
• Experience in IO Timing/ interface budgeting / process margins / corner definitions
• Familiarity with DFT
• Proficient in scripting language (TCL/python).
• Excellent timing and flow debugging skills
• Experience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalence
• Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SOC.
• Hands on experience in reference flows, excellent debugging skills.

Responsibilities

• Oversee full chip and/or subsystem level STA convergence from early stages to signoff.
• Collaborate with logic design and DFT to define and implement constraints for various work modes.
• Contribute to floorplanning and clock planning with top-level perspective.

Skills

ASIC timing constraints

Primetime

IO timing budgeting

DFT familiarity

TCL/Python scripting

Timing debugging

ECO flow for RTL

PPA optimization

Education

Bachelor's or Master's in EE/CS

Tools

PT-DMSA

Job description

Senior Principal Engineer - STA

This position is for Senior Level STA Engineer who will oversee full chip and/or subsystem level STA convergence from early stages to signoff. Taking part in top level floorplan and clock planning. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes including their optimization of runtime.

Key Responsibilities

• Strong experience in ASIC timing constraints generation, validation and timing closure.


• Expertise in Primetime and timing eco (physical aware) using PT-DMSA - full chip and block level


• Experience in IO Timing/ interface budgeting / process margins / corner definitions


• Familiarity with DFT


• Proficient in scripting language (TCL/python).


• excellent timing and flow debugging skills


• Experience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalence.


• Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SOC.


• Proficient in scripting language (TCL/python).


• Hands on experience in reference flows, excellent debugging skills.

Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering

JD for Physical Design Timing

Relevant Experience 07-11 Years – L3 Role : Lead Physical Design Timing Engineer

This position is for Senior Level STA Engineer who will oversee full chip and/or subsystem level STA convergence from early stages to signoff. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes.

Key Responsibilities

• Strong experience in ASIC timing constraints generation, validation and timing closure.


• Expertise in Primetime and timing eco (physical aware) using PT-DMSA - full chip and block level


• Experience in IO Timing/ interface budgeting / process margins / corner definitions


• Familiarity with DFT


• Proficient in scripting language (TCL/python).


• excellent timing and flow debugging skills


• Experience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalence.


• Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SOC.


• Proficient in scripting language (TCL/python).


• Hands on experience in reference flows, excellent debugging skills.