STA Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,400,000 - 2,100,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking an experienced Static Timing Analysis Engineer to drive block-level and full-chip timing analysis, constraint development and sign-off.

The ideal candidate will have hands-on experience with Synopsys PrimeTime and Cadence Tempus, strong STA concepts, OCV/POCV, and a solid background in ASIC Physical Design flows. Python is a plus, and collaboration with PD, RTL, Synthesis, and DFT teams is expected.

Qualifications

• Strong hands-on experience with Synopsys PrimeTime or Cadence Tempus.
• Excellent knowledge of STA concepts and timing methodology.
• Solid understanding of SDC constraints.
• Good knowledge of MCMM, OCV, AOCV and POCV.
• Strong understanding of clock architecture and timing.
• Experience in timing ECO and closure methodologies.
• Good understanding of ASIC Physical Design flow.
• Python knowledge is a plus.

Responsibilities

• Perform Block-Level and Full-Chip Static Timing Analysis.
• Develop, validate and debug SDC timing constraints.
• Analyze Setup, Hold, Recovery and Removal violations.
• Perform MCMM timing analysis across PVT corners.
• Debug timing violations and identify root causes.
• Collaborate with Physical Design, Synthesis, RTL and DFT teams for timing closure.
• Analyze and resolve clock-related timing issues.
• Support timing ECOs and implementation changes.
• Perform timing sign-off and generate detailed timing reports.
• Analyze OCV, AOCV, POCV and derating effects.
• Work on Signal Integrity / Crosstalk-aware timing analysis.
• Support timing closure for high-performance and complex SoC designs.

Skills

Synopsys PrimeTime

Cadence Tempus

STA concepts

SDC constraints

MCMM timing

OCV/AOCV/POCV

clock architecture

timing ECOs

ASIC Physical Design

Python

Education

B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI, or related disciplines

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Education: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI, or related disciplines

Job Description:

We are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in block-level and full-chip timing analysis, timing closure, constraint development, and sign-off.

Key Responsibilities:

• Perform Block-Level and Full-Chip Static Timing Analysis.
• Develop, validate and debug SDC timing constraints.
• Analyze Setup, Hold, Recovery and Removal violations.
• Perform MCMM timing analysis across PVT corners.
• Debug timing violations and identify root causes.
• Work closely with Physical Design, Synthesis, RTL and DFT teams for timing closure.
• Analyze and resolve clock-related timing issues.
• Support timing ECOs and implementation changes.
• Perform timing sign-off and generate detailed timing reports.
• Analyze OCV, AOCV, POCV and derating effects.
• Work on Signal Integrity / Crosstalk-aware timing analysis.
• Support timing closure for high-performance and complex SoC designs.

Required Skills:

• Strong hands-on experience with Synopsys PrimeTime / Cadence Tempus.
• Excellent knowledge of STA concepts and timing methodology.
• Strong understanding of SDC constraints.
• Good knowledge of MCMM, OCV, AOCV and POCV.
• Strong understanding of clock architecture and clock timing.
• Experience in timing ECO and closure methodologies.
• Good understanding of ASIC Physical Design flow.
• Python knowledge is an added advantage.

Preferred:

• Experience in full-chip STA and sign-off.
• Experience with advanced technology nodes.
• Exposure to Signal Integrity, Crosstalk and Low-Power designs.
• Experience working with large and complex SoC designs.