Lead Static Timing Analysis (STA) Engineer

Sykatiya Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Sykatiya Technologies Pvt Ltd in Bengaluru is seeking a Lead Static Timing Analysis (STA) Engineer to drive timing closure for next‑gen ASIC/SoC designs. You will lead multi‑corner, multi‑mode timing signoff across low-power and high-speed clock domains, aligning with RTL, Physical Design, Synthesis, DFT, and CAD teams.

The role demands 8+ years of hands-on STA expertise, strong MCMM and clock topology knowledge, and proficiency in Tcl and Python for flow automation.

Qualifications

• 8+ years hands-on STA across advanced nodes.
• Expert in MCMM timing, AOCV/POCV, crosstalk, IR-drop effects.
• Strong scripting for flows via Tcl and Python.
• Experience with multi-corner, multi-mode timing signoff and ECOs.

Responsibilities

• Define and validate SDC constraints for MCMM timing views.
• Lead block and full-chip STA across PVT corners.
• Drive crosstalk, noise modeling and OCV/POCV analysis.
• Generate and integrate ECOs to meet post-route timing closure.
• Develop signoff methodology and CAD flows with Tcl/Python.

Skills

STA expertise

MCMM timing

Clock topology

Signal integrity

OCV/POCV/IR-drop

ECO flows

Cross-functional collaboration

Education

Electrical Engineering degree (B.S./M.S.)

Tools

Tcl

Python

Job description

We are seeking a highly skilled Lead Static Timing Analysis (STA) Engineer to drive timing closure and signoff for our next‑generation, high-performance ASIC/SoC designs. In this role, you will be technical lead for multi‑corner, multi‑mode (MCMM) timing signoff across ultra‑low power and high‑speed clock domains. You will collaborate closely with RTL Design, Physical Design, Synthesis, DFT, and CAD methodology teams to define timing constraints, debug complex timing paths, and ensure zero‑delay signoff readiness on advanced process nodes.

Key Responsibilities

Technical Leadership & Timing Signoff

• Constraints Management: Define, write, and validate complete SDC (Synopsys Design Constraints) for multi‑mode, multi‑corner (MCMM) timing views, including complex clock domain crossings (CDC) and false/multicycle paths.
• Full‑Chip & Block STA: Lead block‑level and full‑chip timing closure, performing Static Timing Analysis across all process, voltage, and temperature (PVT) corners.
• Signal Integrity & Noise Analysis: Drive crosstalk analysis, glitched clock/data detection, noise analysis, and On‑Chip Variation (OCV/AOCV/POCV) modeling.
• EOC & ECO Generation: Generate, validate, and integrate timing Engineering Change Orders (ECOs) using automated functional/leakage ECO techniques to achieve post‑route timing closure without sacrificing area or power budget.
• Methodology & Flow Setup: Architect and optimize signoff STA methodology, script automation (Tcl/Python), and CAD flow integration for high‑efficiency runtimes.

Cross-Functional Collaboration

• Work with the RTL & Architecture teams to resolve structural timing bottlenecks and critical path constraints early in the design cycle.
• Partner with Physical Design engineers to guide floorplanning, clock tree synthesis (CTS) strategies, and routing optimizations.
• Coordinate with DFT Engineers to set up and close timing for Scan, MBIST, and JTAG modes.
• Interface with EDA vendors to evaluate advanced STA tools and resolve tool/flow anomalies.

Required Qualifications

• Education: Bachelor's or Master's degree in Electrical Engineering, Microelectronics, VLSI Design, or a related technical field.
• Experience: 8+ years of dedicated hands‑on experience in Static Timing Analysis (STA) with a track record of multiple successful tape‑outs on advanced nodes (7nm, 5nm, 3nm).
• In-depth knowledge of MCMM timing analysis, AOCV/POCV, derating methodologies, signal integrity (crosstalk delta-delay and noise), and IR-drop impact on timing.
• Comprehensive understanding of complex clock topologies, clock domain crossings, and asynchronous interfaces.
• Proficient in manual and automated ECO flows (Hold/Setup fixes, leakage recovery).
• Scripting: Advanced proficiency in Tcl and Python for flow development, reporting, and automated timing fix generation.