Principal Engineer – STA

TYLsemi; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

TYLsemi in Bengaluru is seeking a Principal Engineer – STA to lead timing analysis and signoff for advanced ASIC/SOC designs. The role requires deep expertise in static timing analysis, timing closure strategies, and signoff convergence across multi‑clock, multi‑voltage systems.

You will define timing constraints, validate SDCs, and collaborate with RTL, Physical Design, DFT, CTS and CAD teams to achieve timing convergence and successful tape-outs at 7nm/5nm nodes.

Qualifications

• 12+ years of STA and timing signoff experience in ASIC/SOC programs.

Responsibilities

• Lead end-to-end STA and timing signoff for full-chip and subsystem designs.

Skills

STA expertise

Timing signoff

Setup/hold analysis

Scripting: Tcl

Python scripting

Education

Bachelors/Masters in Electronics or VLSI

Tools

Synopsys PrimeTime

Tempus

StarRC

Job description

Role Overview

We are seeking a highly experienced Principal Engineer – STA to lead timing analysis and signoff activities for advanced ASIC/SOC designs. The role requires deep expertise in static timing analysis methodologies, timing closure strategies, and signoff convergence across complex multi‑clock, multi‑voltage, and high‑performance designs. The ideal candidate will provide technical leadership, drive cross‑functional collaboration, and enable successful tape‑outs at advanced technology nodes. 1

What You’ll Do

• Lead end‑to‑end STA and timing signoff activities for full-chip and subsystem‑level designs.
• Drive timing closure across setup, hold, SI, noise, crosstalk, IR‑aware timing, and MMMC scenarios.
• Define timing constraints, validate SDCs, and ensure robust timing methodology execution.
• Collaborate closely with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence.
• Analyze and resolve complex timing violations and critical path bottlenecks.
• Support ECO implementation and signoff verification for advanced node tape‑outs.
• Develop and improve automation flows, scripts, timing dashboards, and methodology enhancements.
• Mentor engineers and lead technical reviews for timing architecture and signoff readiness.

What We’re Looking For

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• 12+ years of experience in STA and timing signoff for ASIC/SOC programs.
• Strong expertise in setup/hold analysis, timing exceptions, CTS interaction, and timing convergence techniques.
• Hands‑on experience with Synopsys PrimeTime, Tempus, StarRC, and related signoff tools.
• Strong understanding of SI, OCV/AOCV/POCV, CDC, low‑power timing methodologies, and advanced node effects.
• Experience with advanced technology nodes such as 7nm, 5nm, or below.
• Strong scripting skills in Tcl, Python, Perl, or Shell scripting.
• Excellent technical leadership, debugging, communication, and stakeholder management skills.

Good to Have

• Experience with package‑aware timing analysis and chiplet architectures.
• Exposure to AI/ML‑driven timing optimization methodologies.
• Familiarity with automotive or high‑reliability SOC design standards.

Success in This Role Looks Like

• Successful timing closure and signoff delivery for complex SOC tape‑outs.
• Efficient management of timing convergence with minimal ECO impact.
• Improved STA methodology scalability, automation, and execution efficiency.
• Strong technical influence, mentoring contribution, and cross‑functional leadership.