Senior Engineer – Static Timing Analysis (STA)

TylSemi; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

TylSemi is seeking a highly skilled Senior Engineer – Static Timing Analysis (STA) to join its Physical Design team in Bengaluru, India. In this role, you will drive timing closure and signoff activities for complex SoC designs. You will collaborate with synthesis, place-and-route, CTS, and ECO teams to ensure robust timing convergence.

The ideal candidate should have a Bachelor's or Master's degree in Electronics or Electrical Engineering, with at least 5 years of experience in STA and strong understanding of timing analysis concepts. The position offers opportunities to work with the latest technology nodes.

Qualifications

• 5+ years of experience in STA, timing closure, or physical design signoff roles.
• Strong understanding of STA concepts including setup/hold analysis, clock skew, jitter, and timing exceptions.
• Hands-on experience with Synopsys PrimeTime and timing signoff methodologies.

Responsibilities

• Perform block-level and full-chip static timing analysis for setup, hold, recovery, removal, and noise checks.
• Drive timing closure by debugging and resolving timing violations across multiple modes and corners.
• Develop and validate timing constraints, including SDC generation and timing exception management.

Skills

Static Timing Analysis

Timing Closure

Tape-out Delivery

Debugging Timing Violations

Automation Scripting (Tcl, Perl, Python, Shell)

Education

Bachelor’s or Master’s degree in Electronics or Electrical Engineering

Tools

Synopsys PrimeTime

Job description

Senior Engineer – Static Timing Analysis (STA)

We are seeking a highly skilled Senior Engineer – Static Timing Analysis (STA) to join the Physical Design team. In this role, you will be responsible for driving timing closure and signoff activities for complex SoC designs across advanced technology nodes. You will collaborate with synthesis, place‑and‑route, CTS, and ECO teams to ensure robust timing convergence and successful tape‑out delivery.

Responsibilities

• Perform block‑level and full‑chip static timing analysis for setup, hold, recovery, removal, and noise checks.
• Drive timing closure by debugging and resolving timing violations across multiple modes and corners.
• Develop and validate timing constraints, including SDC generation and timing exception management.
• Work closely with synthesis, CTS, P&R, and ECO teams to optimize timing, area, and power.
• Execute MMMC timing analysis using industry‑standard STA methodologies.
• Perform ECO implementation and timing signoff for advanced‑node designs.
• Support tape‑out activities and ensure clean timing signoff delivery.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a VLSI‑related discipline.
• 5+ years of experience in STA, timing closure, or physical design signoff roles.
• Strong understanding of STA concepts including setup/hold analysis, clock skew, jitter, and timing exceptions.
• Hands‑on experience with Synopsys PrimeTime and timing signoff methodologies.
• Good understanding of synthesis, CTS, place‑and‑route, and ECO flows.
• Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow enhancement.

Desired Skills

• Experience with advanced nodes such as 7nm, 5nm, or below.
• Exposure to low‑power methodologies including UPF/CPF and power‑aware STA.
• Knowledge of SI/noise analysis, OCV/AOCV/POCV methodologies, and timing convergence techniques.

Success in This Role Looks Like

• Achieving timing closure with clean setup and hold signoff across all modes and corners.
• Efficiently resolving complex timing violations with minimal impact on area and power.
• Improving STA productivity through automation and methodology enhancements.
• Successful support of tape‑out milestones with high‑quality timing signoff.

Location: [Specify location if applicable]