Senior Principal Engineer - STA

Larsen & Toubro; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Larsen & Toubro in Bengaluru seeks a Senior STA Engineer to oversee chip and subsystem level timing convergence from early stages to signoff. You will work with logic design and DFT teams to implement constraints for various work modes and optimize runtime.

Role involves floorplanning, clock planning, ECO generation, and automation to improve PPA in SOC design, with strong scripting in TCL/Python and debugging skills.

Qualifications

• Experience in ASIC timing constraints generation, validation and timing closure.
• Expertise in Primetime and timing eco (physical aware) using PT-DMSA at full chip and block level.
• Experience in IO Timing, interface budgeting, process margins and corner definitions.

Responsibilities

• Lead timing constraints generation, validation and closure for ASIC/SoCs.
• Utilize Primetime and PT-DMSA for full-chip and block-level timing eco.
• Coordinate IO timing, budgeting, margins, and corner case definitions.

Skills

ASIC Timing Constraints

Primetime

PT-DMSA

IO Timing & Budgeting

DFT

TCL/Python scripting

ECO Flows

PPA Optimization

Debugging & Reference Flows

Education

Bachelor's/Master's in Computer/Electronics/Electrical Engineering

Tools

Primetime tooling

PT-DMSA

Job description

Job Description:

This position is for Senior Level STA Engineer who will oversee full chip and/or subsystem level STA convergence from early stages to signoff. Taking part in top level floorplan and clock planning. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes including their optimization of runtime.

Key Responsibilities

• Strong experience in ASIC timing constraints generation, validation and timing closure.
• Expertise in Primetime and timing eco (physical aware) using PT-DMSA - full chip and block level
• Experience in IO Timing/ interface budgeting / process margins / corner definitions
• Familiarity with DFT
• Proficient in scripting language (TCL/python).
• excellent timing and flow debugging skills
• Experience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalence.
• Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SOC.
• Proficient in scripting language (TCL/python).
• Hands on experience in reference flows, excellent debugging skills.

Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering

JD for Physical Design Timing

Relevant Experience 07-11 Years – L3

Role : Lead Physical Design Timing Engineer

Key Responsibilities

• Strong experience in ASIC timing constraints generation, validation and timing closure.
• Expertise in Primetime and timing eco (physical aware) using PT-DMSA - full chip and block level
• Experience in IO Timing/ interface budgeting / process margins / corner definitions
• Familiarity with DFT
• Proficient in scripting language (TCL/python).
• excellent timing and flow debugging skills
• Experience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalence.
• Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SOC.
• Proficient in scripting language (TCL/python).
• Hands on experience in reference flows, excellent debugging skills.

Requirements: