Staff Engineer – Physical Design (STA)

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking an experienced ASIC/SoC STA engineer to own block/full-chip STA, timing convergence, and signoff for first-pass silicon. You will develop and validate SDC constraints, ECOs, and timing budgets, collaborate with RTL, Synthesis, PD, CTS, DFT and Architecture teams, and drive low-power timing analysis and methodology improvements.

The ideal candidate has 8–12 years of hands-on experience and deep knowledge of 7nm/5nm/3nm flows, with scripting in

Qualifications

• 8–12 years of hands-on experience in ASIC/SoC Static Timing Analysis.
• Expert in PrimeTime and Cadence Tempus.
• Strong expertise in MMMC, SI, Crosstalk, OCV/AOCV/POCV, LVF, CRPR, ECO, SDC, Timing Constraints, and Signoff.

Responsibilities

• Drive block/full-chip STA across MMMC scenarios from synthesis through tapeout.
• Own timing closure, ECO implementation, and signoff for setup, hold, SI, Crosstalk, OCV/AOCV/POCV, LVF, and CRPR.
• Develop and validate SDC constraints, timing exceptions, clock definitions, and hierarchical timing budgets.
• Collaborate with RTL, Synthesis, Physical Design, CTS, DFT, and Architecture teams to resolve critical timing bottlenecks.
• Drive Low-Power (UPF/CPF) timing analysis, CDC/RDC awareness, and timing methodology improvements.
• Develop Tcl/Python automation to improve STA productivity and signoff quality.

Skills

ASIC/SoC STA

Timing constraints & signoff

RTL/Synthesis/Physical Design

Tools

PrimeTime

Cadence Tempus

Job description

Own block/full-chip STA and timing closure for high-performance SoCs across advanced technology nodes. Drive timing convergence and signoff to enable first-pass silicon success.

What You'll Do

• Drive block/full-chip STA across MMMC scenarios from synthesis through tapeout.
• Own timing closure, ECO implementation, and signoff for setup, hold, SI, Crosstalk, OCV/AOCV/POCV, LVF, and CRPR.
• Develop and validate SDC constraints, timing exceptions, clock definitions, and hierarchical timing budgets.
• Collaborate with RTL, Synthesis, Physical Design, CTS, DFT, and Architecture teams to resolve critical timing bottlenecks.
• Drive Low-Power (UPF/CPF) timing analysis, CDC/RDC awareness, and timing methodology improvements.
• Develop Tcl/Python automation to improve STA productivity and signoff quality.

What You Bring

• 8–12 years of hands-on experience in ASIC/SoC Static Timing Analysis.
• Expert in PrimeTime and/or Cadence Tempus.
• Strong expertise in MMMC, SI, Crosstalk, OCV/AOCV/POCV, LVF, CRPR, ECO, SDC, Timing Constraints, and Signoff.
• Good understanding of RTL, Synthesis, CTS, Physical Design, and advanced-node implementation (7nm/5nm/3nm).
• Experience with scripting using Tcl; Python/Perl is a plus.

Preferred

• Experience with CPU, GPU, AI/ML, Networking, Mobile, or Automotive SoCs.
• Exposure to EM/IR, Physical Signoff, and Fusion Compiler/ICC2/Innovus flows.

We're looking for engineers who can solve complex timing challenges, architect scalable STA methodologies, and deliver robust full-chip timing signoff for next-generation SoCs.