Technical Lead - STA

BITSILICA; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Bitsilica is seeking an experienced Static Timing Analysis (STA) Engineer to lead timing sign-off for complex SoC designs in Bengaluru. You will perform block and full-chip STA, develop timing constraints, and collaborate with PD, RTL, and Architecture teams to drive design closure.

The ideal candidate has hands-on PrimeTime experience, deep understanding of SDC constraints, and strong debugging skills to fix setup/hold violations and support ECOs for tape-out.

Qualifications

• Experience in static timing analysis for complex SoCs.
• Strong understanding of timing constraints (SDC).
• Proficiency with timing closure across corners and modes.

Responsibilities

• Perform block and full-chip Static Timing Analysis for complex SoC designs.
• Develop and validate timing constraints (SDC).
• Drive timing closure across different corners and modes.
• Analyze and debug setup/hold violations.
• Work closely with Physical Design, RTL, and Architecture teams.
• Support ECO implementation for timing fixes.
• Handle timing sign-off for tape-out.
• Perform clock tree and timing path analysis.
• Strong expertise in Static Timing Analysis (STA).
• Hands-on experience with Synopsys PrimeTime.
• Strong understanding of timing constraints (SDC).
• Experience in timing closure and sign-off.
• Understanding of clocking architecture and CDC concepts.
• Exposure to advanced technology nodes.
• Good understanding of Physical Design flow.

Skills

Static Timing Analysis

Timing closure

Constraints development

Clocking architecture

Synopsys PrimeTime

Debugging

Timimg analysis

Tools

Synopsys PrimeTime

Job description

Notice Period: Immediate to 30 Days Preferred

We are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in timing sign-off for complex SoC designs. The candidate should have hands-on experience in timing closure, constraints development, and working closely with PD and RTL teams to achieve design closure.

• Perform block and full-chip Static Timing Analysis for complex SoC designs


• Develop and validate timing constraints (SDC)


• Drive timing closure across different corners and modes


• Analyze and debug setup/hold violations


• Work closely with Physical Design, RTL, and Architecture teams


• Support ECO implementation for timing fixes


• Handle timing sign-off for tape-out


• Perform clock tree and timing path analysis


• Strong expertise in Static Timing Analysis (STA)


• Hands-on experience with Synopsys PrimeTime


• Strong understanding of timing constraints (SDC)


• Experience in timing closure and sign-off


• Understanding of clocking architecture and CDC concepts


• Exposure to advanced technology nodes


• Good understanding of Physical Design flow

Good to Have

• Experience with CPU/GPU or high-performance SoC designs


• Knowledge of Low Power (UPF/CPF)


• Exposure to Synthesis and PD flow


• Experience in ECO and sign-off flows


• 10+ years of experience in STA / Timing Analysis


• Strong debugging and problem-solving skills


• Ability to work independently and drive timing closure