Senior STA Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking a Senior Full-Chip Static Timing Analysis (STA) Engineer to own timing signoff and convergence for large high-performance SoCs across advanced nodes. You will partner with PD, RTL, DFT, Synthesis, Library and CAD teams to achieve first-pass silicon success.

Responsibilities include owning full-chip STA signoff across modes and MCMM scenarios, driving timing closure for setup/hold/clock gating, performing advanced timing analyses, and developing SDC

Qualifications

• 7–10 years of hands-on experience in Full-Chip STA and Timing Signoff for complex ASIC/SoC designs.

Responsibilities

• Own full-chip STA signoff across all functional modes, PVT corners, and MCMM scenarios.
• Drive timing closure for setup, hold, recovery, removal, minimum pulse width, clock gating, and asynchronous timing checks.
• Perform advanced timing analysis using OCV, AOCV, POCV, LVF, CRPR, and variation-aware signoff methodologies.
• Lead full-chip timing convergence by analysing critical timing paths and driving closure with PD, RTL, and Architecture teams.
• Debug complex timing issues related to clock architecture, long interconnects, hierarchical interfaces, timing exceptions, and generated clocks.
• Perform Signal Integrity (SI), Crosstalk, Noise, and Delta Delay analysis and drive clean timing signoff.
• Develop, validate, and maintain SDC constraints, ensuring complete timing coverage across the chip.
• Execute and validate timing ECOs while balancing performance, power, and area (PPA).
• Correlate timing across Synthesis, Place & Route, and Signoff environments to ensure silicon accuracy.
• Drive hierarchical and top-level timing integration, interface timing closure, and partition-level signoff.
• Work closely with Physical Design teams during CTS, routing, post-route optimization, and final signoff.
• Develop automation using Tcl, Python, or Perl to improve signoff productivity, regression, QoR analysis, and reporting.
• Support tapeout readiness through comprehensive timing signoff reviews and cross-functional design closure.

Skills

Full-Chip STA

Timing signoff

Critical path analysis

Clock distribution

Scripting (Tcl, Python, Perl)

Synthesis/PD/RTL collaboration

Noise/Signal Integrity (SI)

Education

B.E./B.Tech/M.E./M.Tech in Electronics or Electrical Engineering

Tools

ICC2/Fusion Compiler

Cadence Innovus

SDF/LEF/DEF

Job description

We are looking for a Senior Full-Chip Static Timing Analysis (STA) Engineer to own timing signoff and closure for large, high-performance SoCs across advanced technology nodes. You will be responsible for driving full-chip timing convergence from post-CTS through tapeout, partnering with Physical Design, RTL, DFT, Synthesis, Library, and CAD teams to achieve first-pass silicon success.

Responsibilities

• Own full-chip STA signoff across all functional modes, PVT corners, and MCMM scenarios.
• Drive timing closure for setup, hold, recovery, removal, minimum pulse width, clock gating, and asynchronous timing checks.
• Perform advanced timing analysis using OCV, AOCV, POCV, LVF, CRPR, and variation-aware signoff methodologies.
• Lead full-chip timing convergence by analysing critical timing paths and driving closure with PD, RTL, and Architecture teams.
• Debug complex timing issues related to clock architecture, long interconnects, hierarchical interfaces, timing exceptions, and generated clocks.
• Perform Signal Integrity (SI), Crosstalk, Noise, and Delta Delay analysis and drive clean timing signoff.
• Develop, validate, and maintain SDC constraints, ensuring complete timing coverage across the chip.
• Execute and validate timing ECOs while balancing performance, power, and area (PPA).
• Correlate timing across Synthesis, Place & Route, and Signoff environments to ensure silicon accuracy.
• Drive hierarchical and top-level timing integration, interface timing closure, and partition-level signoff.
• Work closely with Physical Design teams during CTS, routing, post-route optimization, and final signoff.
• Develop automation using Tcl, Python, or Perl to improve signoff productivity, regression, QoR analysis, and reporting.
• Support tapeout readiness through comprehensive timing signoff reviews and cross-functional design closure.

Required Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or related discipline.
• 7–10 years of hands-on experience in Full-Chip STA and Timing Signoff for complex ASIC/SoC designs.
• Proven experience closing timing on large-scale SoCs through multiple successful tapeouts.

Technical Expertise

Timing Signoff

• Full-chip timing signoff
• MCMM timing analysis
• Setup/Hold closure
• OCV, AOCV, POCV, LVF
• Timing ECO implementation
• MMMC methodology
• SDC development and constraint validation

Physical Design Awareness

• CTS optimization
• Clock distribution and skew management
• Post-route timing optimization
• RC extraction and parasitic analysis
• LEF/DEF, SPEF, SDF
• Strong understanding of ICC2/Fusion Compiler or Cadence Innovus flows

Scripting & Automation

• Tcl
• Python
• Perl
• Shell scripting
• Advanced FinFET nodes (7nm, 5nm, 4nm, 3nm and below)
• High-performance CPU, GPU, AI Accelerator, Networking, or Datacenter SoCs

Preferred Qualifications

• Expertise in full-chip timing architecture, partition integration, and top-level signoff methodologies.
• Experience driving timing closure across 100M+ instance designs.
• Strong understanding of low-power timing (UPF/CPF), hierarchical STA, and timing correlation with silicon.
• Proven ability to drive cross-functional timing closure with minimal supervision in a fast-paced product development environment.

What You'll Bring

• Deep expertise in full-chip timing signoff and advanced STA methodologies.
• Strong analytical and debugging skills with a data-driven approach to timing closure.
• Ownership mindset with the ability to lead timing closure for complex SoCs from implementation through tapeout.
• Passion for building industry-leading silicon with uncompromising quality and performance.