Design Engineer

M/s Angel and Genie (Talent Search Company); Bengaluru; On-site; INR 800,000 - 1,500,000; Full time

Job summary

An established industry player seeks talented RTL Engineers and Leads to join their dynamic team. This exciting role involves developing RTL designs for ASIC and SoC projects while collaborating with architects and physical design teams to optimize performance, power, and area metrics. The ideal candidate will have over 4 years of hands-on experience in RTL design and integration with high-speed IPs, along with strong analytical and problem-solving skills. Join this innovative firm to contribute to cutting-edge projects in the IT system custom software development sector and make a significant impact in the field.

Qualifications

• 4+ years of experience in RTL design and integration with High-speed IPs.
• Proficient in Verilog/System Verilog/Chisel coding and simulation tools.

Responsibilities

• Develop RTL design for ASIC and SoC projects and optimize for performance.
• Collaborate with architects and design teams to achieve goals.

Skills

RTL Design

Verilog/System Verilog/Chisel

Linting

CDC

Synthesis

Analytical Skills

Problem-Solving Skills

Communication Skills

Teamwork Abilities

Education

Bachelor's in Engineering

Master's in Engineering

Tools

Questa

VCS

Synopsys Spyglass

DC

Job description

M/s Angel and Genie (Talent Search Company) Bengaluru, Karnataka, India

Recruitment Coordinator at Angel and Genie

Our Client is MNC, selected candidates will be on the roles of client, they looking for RTL Design Engineer.

We are looking for talented RTL Engineers and Leads with expertise in High-speed IPs and CPUs. The ideal candidate will have over 4 years and above experience in uArch design, RTL coding, quality checks (Linting, CDC, Synthesis) and integration of High-speed IPs/CPUs in complex ASICs/SoCs.

Key Responsibilities:

1. Develop RTL design/coding for ASIC and SoC projects.
2. Collaborate closely with architects and physical design teams to achieve design goals.
3. Optimize RTL designs for performance, power, and area (PPA) metrics.
4. Participate in design reviews and contribute to the overall design methodology improvements.
5. Integration of High-speed IPs (Controller, Phy).
6. Support post-silicon validation and debug activities as needed.

Qualifications:

1. 4-15 years of hands-on experience in RTL design, Integration with High-speed IPs.
2. Proficiency in Verilog/System Verilog/Chisel coding and familiarity with RTL simulation tools (e.g., Questa, VCS).
3. Solid understanding of ASIC and SoC design flows and methodologies.
4. Good experience and knowledge in integrating one or more of the following high-speed IPs/Interfaces is a must: DDR (LPDDR 4/5/6, GDDR6), PCIe Gen 4/5/6, CXL 2/3, UCIe, Ethernet 100G/200G/400G/800G, Coherent Interconnects like ARM CMN, CPUs like ARM Cortex X4, A7xx, A5xx, A7x, A5x series, Neoverse N2.
5. Good knowledge in one or more of the following protocols/specifications is a must: PCIe Gen4/5/6, CXL 2/3, UCIe, Ethernet, AMBA CHI.
6. Good experience and knowledge in Linting, CDC and Synthesis.
7. Good knowledge in clocking, reset and power.
8. Experience with linting, CDC, synthesis and timing analysis tools (e.g., Synopsys spyglass, DC).
9. Strong analytical and problem-solving skills.
10. Excellent communication and teamwork abilities.

Education

Doctorate: Doctorate Not Required

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Design

Industries

IT System Custom Software Development