Sr. Design Engineer 2

Tessolve; Bengaluru; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

Tessolve in Bengaluru, India, seeks an experienced RTL design engineer to contribute to ASIC/SoC development. You will craft micro-architecture specs, design and implement RTL in Verilog/SystemVerilog, and collaborate with verification teams on testbenches.

The role covers synthesis, linting, CDC checks, STA, DFT support, IP integration, and ensuring power, performance, and area targets while working with firmware and validation teams.

Qualifications

• 5–8 years of hands‑on RTL design for ASIC/SoC required.
• Strong expertise in Verilog/SystemVerilog and micro‑architecture.
• Experience with synthesis, STA, CDC, and low‑power design concepts.
• Familiarity with AMBA protocols (AXI/AHB/APB) preferred.
• Experience in IP integration and SoC architecture.
• Experience with industry‑standard EDA tools (Synopsys, Cadence, Mentor).
• Knowledge of scripting languages is a plus (Perl/Python/TCL).
• Familiarity with AMBA protocols preferred.

Responsibilities

• Develop micro-architecture specifications based on system requirements.
• Design and implement RTL using Verilog/SystemVerilog.
• Perform RTL coding, linting, CDC checks, and synthesis.
• Work closely with verification teams for testbench support and debug.
• Participate in design reviews and provide technical solutions.
• Perform block-level and SoC-level integration.
• Support STA, DFT, and physical design teams during implementation.
• Analyze and debug functional and timing issues.
• Ensure design meets power, performance, and area (PPA) targets.
• Collaborate with cross-functional teams including firmware and validation.

Skills

RTL design

Verilog/SystemVerilog

Micro-architecture

Synthesis

STA

CDC

Low-power design

EDA tools

Debugging

Scripting (Perl/Python/TCL)

AMBA AXI/AHB/APB

IP integration

SoC architecture

Education

B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / VLSI

Tools

Synopsys

Cadence

Mentor

Job description

Key Responsibilities

• Develop micro-architecture specifications based on system requirements.
• Design and implement RTL using Verilog/SystemVerilog.
• Perform RTL coding, linting, CDC checks, and synthesis.
• Work closely with verification teams for testbench support and debug.
• Participate in design reviews and provide technical solutions.
• Perform block-level and SoC-level integration.
• Support STA, DFT, and physical design teams during implementation.
• Analyze and debug functional and timing issues.
• Ensure design meets power, performance, and area (PPA) targets.
• Collaborate with cross-functional teams including firmware and validation.

Key Responsibilities

• Develop micro-architecture specifications based on system requirements.
• Design and implement RTL using Verilog/SystemVerilog.
• Perform RTL coding, linting, CDC checks, and synthesis.
• Work closely with verification teams for testbench support and debug.
• Participate in design reviews and provide technical solutions.
• Perform block-level and SoC-level integration.
• Support STA, DFT, and physical design teams during implementation.
• Analyze and debug functional and timing issues.
• Ensure design meets power, performance, and area (PPA) targets.
• Collaborate with cross-functional teams including firmware and validation.

Required Skills & Qualifications

• 5–8 years of hands‑on experience in RTL design for ASIC/SoC.
• Strong expertise in Verilog/SystemVerilog.
• Experience in micro‑architecture and high‑speed digital design.
• Good understanding of synthesis, STA, CDC, and low‑power design concepts.
• Experience with industry‑standard EDA tools (e.g., Synopsys, Cadence, Mentor).
• Strong debugging and problem‑solving skills.
• Knowledge of scripting languages (Perl/Python/TCL) is a plus.
• Familiarity with AMBA protocols (AXI/AHB/APB) preferred.
• Experience in IP integration and SoC architecture.

Preferred Qualifications

• Experience in high‑speed interfaces (PCIe, USB, Ethernet, DDR, etc.).
• Exposure to low‑power design techniques (UPF/CPF).
• Experience in 7nm/5nm or advanced technology nodes is an advantage.
• Knowledge of FPGA prototyping is a plus.

Education

• B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / VLSI / related field.