Senior Memory Layout Engineer

LeadSoc Technologies Pvt Ltd; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Hyderabad, India is seeking a Senior Memory Layout Engineer with 5–10 years of hands‑on experience in memory circuit layout and physical implementation. You will work closely with circuit design, technology, and verification teams to deliver DRC/LVS‑clean layouts.

Responsibilities include developing custom memory layouts (SRAM/ROM), bitcells, and periphery, ensuring matching, symmetry, and parasitic reduction, and supporting PEX and post‑layout simulations.

Qualifications

• 5–10 years of memory/custom IC layout experience.
• Proficient in SRAM/memory macro layouts.
• Strong CMOS layout concepts and design rules.
• Experience with DRC/LVS debugging and verification.
• Knowledge of FinFET/advanced-node layouts preferred.
• Scripting exposure in SKILL, Python, Tcl, or Shell is a plus.

Responsibilities

• Develop custom layouts for memory circuits including SRAM and ROM.
• Execute block and full memory layout from schematic to DRC/LVS-clean database.
• Collaborate with circuit designers for layout optimization and parasitic reduction.
• Support PEX and post-layout simulation activities.
• Ensure adherence to foundry PDK and layout methodologies.
• Conduct layout checks for symmetry, shielding, and density.
• Participate in tapeout reviews and continuous layout improvements.

Skills

Memory layout

SRAM layout

Parasitics and matching

Scripting (Python/Tcl/SKILL)

DRC/LVS debugging

Layout optimization

Tools

Cadence Virtuoso

Calibre

Job description

Senior Memory Layout Engineer

Location: Hyderabad, India

Experience: 5–10 Years

Role Overview:

We are looking for experienced Senior Memory Layout Engineers with strong hands‑on expertise in custom layout and physical implementation of memory circuits. The role involves working closely with circuit design, technology, and verification teams to deliver high-quality, DRC/LVS-clean memory layouts.

Key Responsibilities:

• Develop custom layouts for memory circuits including SRAM, ROM, Register File, and memory periphery.
• Execute block-level and full-memory layout from schematic/netlist to DRC/LVS-clean database.
• Work on layout of bitcells, sense amplifiers, pre-charge circuits, decoders, write/read paths, and peripheral circuits.
• Perform matching, symmetry, shielding, common-centroid, and parasitic‑aware layout as applicable.
• Debug and resolve DRC, LVS, ERC, antenna, density, and connectivity issues.
• Collaborate with circuit designers on layout optimization, PPA, matching, and parasitic reduction.
• Support PEX and post‑layout simulation activities.
• Ensure adherence to foundry PDK, design rules, and layout methodologies.
• Participate in design reviews, tapeout activities, and continuous layout methodology improvements.

Required Skills:

• 5–10 years of relevant experience in Memory / Custom IC Layout.
• Strong hands‑on experience with SRAM and/or memory macro layout.
• Good understanding of CMOS layout concepts, device matching, parasitics, and design rules.
• Experience with industry‑standard tools such as Cadence Virtuoso, Calibre, or equivalent.
• Strong expertise in DRC/LVS debugging and physical verification.
• Understanding of FinFET/advanced-node layout concepts is preferred.
• Good scripting/automation exposure using SKILL, Python, Tcl, or Shell is an advantage.
• Strong analytical, debugging, and cross‑functional collaboration skills.

Preferred

• Experience with high-density memory macros and advanced-node technologies.
• Exposure to full-custom layout, PEX, EM/IR, and reliability checks.
• Experience working in a tapeout‑driven semiconductor environment.