Memory Layout Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd is hiring Memory Layout Engineers in Bangalore to work on cutting-edge semiconductor technologies. The role requires 4+ years of memory layout experience on advanced nodes and strong expertise in physical verification, DRC/LVS, and DFY/DFM practices.

Candidate should be proficient in scripting with Perl, Shell, TCL, or SKILL and familiar with memory block design involving bit cell arrays and decoders. Join a team focused on cutting-edge memory solutions.

Qualifications

• 4+ years of memory layout experience on advanced nodes.
• Expertise in TSMC or similar nodes (2nm/3nm/5nm).
• Strong understanding of physical verification, layout methodologies, and design flows.
• Scripting knowledge is a plus.

Responsibilities

• Design memory layouts for building blocks including Bit Cell Arrays, Row/Column Decoders, Sense Amplifiers, and I/O blocks.
• Integrate top-level memory layouts and ensure compatibility across blocks.
• Perform physical verification using DRC and LVS.
• Ensure layouts meet DFM and DFY requirements.
• Analyze layouts for power and signal integrity.
• Develop and maintain automation scripts using Perl, Shell, TCL, or SKILL.

Skills

Memory layout

Physical verification

Power integrity

Signal integrity

Semiconductor design flows

Scripting

Tools

Perl

Shell

TCL

SKILL

Job description

? We're Hiring | Memory Layout Engineers ?

We're looking for experienced Memory Layout Engineers to join our team and work on cutting-edge semiconductor technologies.

Experience: 4+ Years

Location: Bangalore

Key Responsibilities:

• Design memory layouts for various building blocks, including:
• Bit Cell Arrays ,Row Decoders, Column Decoders, Sense Amplifiers, Input/Output (I/O) Blocks
• Integrate top-level memory layouts.
• Perform physical verification using DRC and LVS.
• Ensure layouts comply with Design for Manufacturability (DFM) and Design for Yield (DFY) requirements.
• Analyze layouts for power integrity and signal integrity.
• Develop and maintain automation scripts using PERL, Shell, TCL, or SKILL.

Required Skills:

• Strong hands-on experience in Memory Layout for advanced technology nodes.
• Expertise in TSMC and/or other process technologies with lower nodes (2nm/3nm/5nm).
• Solid understanding of physical verification, layout methodologies, and semiconductor design flows.
• Scripting knowledge is an added advantage.