Memory Design Engineer: Noida

Incise Infotech; Dadri; On-site; INR 1,500,000 - 2,400,000; Full time

Job summary

Incise Infotech is seeking an experienced Memory Design & Characterization Engineer with strong expertise in SRAM memory design, characterization, validation, and library generation. The candidate should have hands-on SPICE simulations, memory characterization, and sign-off activities in deep submicron technologies.

Required skills include SRAM design and characterization, memory circuit design, PEX, NLDM/CCS/CCST library characterization, and scripting for automation.

Qualifications

• Experience in SRAM memory design, characterization and validation in deep submicron tech.
• Hands-on SPICE simulations, writing decks, stimuli and test vectors.
• Experience with layout parasitic extraction (PEX) and memory library sign-off QA.
• Proficiency in memory circuit design concepts and NLDM/CCS/CCST library characterization.
• Automation via scripting for memory design/workflows is a plus.

Skills

Memory domain

SRAM

SRAM design

SRAM characterization

validation

Memory circuit design

SPICE

PEX

SPICE tools

Waveform viewers

Library characterization

Memory library generation

sign‑off QA

Sanity tests

Scripting

Memory Layout Engineer

Job description

Job Description

We are looking for an experienced Memory Design & Characterization Engineer with strong expertise in SRAM memory design, characterization, validation, and library generation. The ideal candidate should have hands‑on experience working with deep submicron technologies, SPICE simulations, memory characterization, and sign‑off activities.

Required Skills

• Strong experience in the Memory domain, preferably SRAM.
• Hands‑on experience in SRAM memory characterization, design, and validation.
• Good understanding of memory circuit design and operation.
• Strong knowledge of SPICE simulations, including writing SPICE decks, stimuli, and test vectors.
• Experience with layout parasitic extraction (PEX) and deep submicron technology challenges.
• Hands‑on experience with fast SPICE/simulator tools.
• Strong debugging skills with experience using waveform viewers.
• Experience with NLDM and CCS/CCST library characterization.
• Hands‑on experience in standard-cell/memory library generation and sign‑off QA checks.
• Experience validating libraries through sanity/tight‑stimulus runs.
• Scripting/programming knowledge for automation is highly preferred. We are looking for an experienced Memory Layout Engineer with strong expertise in custom layout design, memory leafcell layout, FinFET technology, and physical verification. The ideal candidate should have hands‑on experience in designing optimized memory layouts and integrating memory leafcell libraries at the top level.