Memory Layout Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd invites an experienced Memory/Custom Layout Engineer to join our Bengaluru team. You will implement memory layout blocks, verify design integrity, and optimize physical layouts across SRAM/ROM/NVM blocks.

The role emphasizes hands-on layout work, DRC/LVS/ERC, and close collaboration with design teams to meet PPA targets using Cadence Virtuoso and Calibre. Prior knowledge of memory compiler techniques and scripting is a plus.

Qualifications

• BE/B.Tech/M.Tech in ECE, EE, VLSI or related field.
• Hands-on memory/layout experience including memory arrays and verification.
• Familiarity with Cadence Virtuoso and Calibre.

Responsibilities

• Hands-on experience in Memory Layout / Custom Layout for SRAM, ROM, NVM or Memory Compiler blocks.
• Experience in Bitcell, Memory Array, Row/Column Decoder, Sense Amplifier, I/O and Peripheral layouts.
• Strong knowledge of Floorplanning, Routing, Hierarchical Layout & Layout Optimization.
• Hands-on experience with DRC, LVS, ERC, Antenna, EM/IR and Physical Verification.
• Good understanding of CMOS/FinFET technologies, layout rules, matching, parasitics and PPA optimization.
• Proficiency in Cadence Virtuoso/Virtuoso XL and preferably Calibre.
• Knowledge of Memory Compiler / Tiling / Automation is an added advantage.
• Exposure to SKILL / Perl / TCL / Shell scripting is a plus.

Skills

Memory layout

Memory array

Layout optimization

DRC/LVS/ERC

Floorplanning

Physical verification

Education

BE/B.Tech/M.Tech in ECE/EE/VLSI

Tools

Cadence Virtuoso

Virtuoso XL

Calibre

TCL scripting

Memory Compiler

Job description

Notice Period: Immediate Joiners / Short Notice Preferred

Key Responsibilities:

• Hands-on experience in Memory Layout / Custom Layout for SRAM, ROM, NVM or Memory Compiler blocks.
• Experience in Bitcell, Memory Array, Row/Column Decoder, Sense Amplifier, I/O and Peripheral layouts.
• Strong knowledge of Floorplanning, Routing, Hierarchical Layout & Layout Optimization.
• Hands-on experience with DRC, LVS, ERC, Antenna, EM/IR and Physical Verification.
• Good understanding of CMOS/FinFET technologies, layout rules, matching, parasitics and PPA optimization.
• Proficiency in Cadence Virtuoso/Virtuoso XL and preferably Calibre.
• Knowledge of Memory Compiler / Tiling / Automation is an added advantage.
• Exposure to SKILL / Perl / TCL / Shell scripting is a plus.

Education:

BE/B.Tech/M.Tech in ECE, EE, VLSI, Microelectronics or related field.

Ideal Candidate:

Memory/Custom Layout Engineer with strong hands-on implementation and physical verification experience. Current industry postings similarly emphasize Virtuoso, DRC/LVS, memory arrays and physical verification.