Memory Layout Engineer

leadIC Design Pvt Ltd; Bengaluru; On-site; INR 1,000,000 - 2,000,000; Full time

Job summary

A semiconductor design company in Bangalore is seeking an experienced Memory Layout Engineer to execute full-custom layout design for memory IPs such as SRAM and ROM. The ideal candidate should have hands-on expertise in advanced FinFET technologies from TSMC and collaborate closely with circuit design and validation teams to ensure optimal performance. A degree in Electronics or VLSI and 3–10 years of relevant experience are required.

Qualifications

• 3–10 years of hands-on layout experience in advanced TSMC nodes.
• Strong layout debugging and problem-solving skills.
• Ability to work effectively in a cross-functional environment.

Responsibilities

• Execute full-custom layout design for memory blocks using industry-standard EDA tools.
• Ensure design rule compliance, layout vs schematic, antenna checks, and ERC sign-offs.
• Collaborate with circuit designers to implement optimal layout topology.
• Optimize layout for matching, symmetry, and parasitic control.
• Run layout extraction and assist with post-layout simulation and debugging.

Skills

TSMC 3nm/5nm/7nm FinFET technologies

Cadence Virtuoso

Calibre

ICV

Synopsys Custom Compiler

Basic proficiency in SKILL, Tcl, or Python

Memory types (SRAM/ROM/CAM/Register File)

Education

B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or related field

Job description

Job Summary:

We are seeking an experienced Memory Layout Engineer with hands‑on expertise in advanced FinFET nodes (3nm / 5nm / 7nm) from TSMC. The ideal candidate will be responsible for full‑custom layout design and validation of memory IPs such as SRAM, ROM, and register files. The role involves close collaboration with circuit design, verification, and DRC/LVS teams to ensure best‑in‑class performance and yield.

Key Responsibilities:

• Execute full‑custom layout design for memory blocks (SRAM, ROM, CAM, RF, etc.) using industry‑standard EDA tools.
• Ensure design rule compliance (DRC), layout vs schematic (LVS), antenna checks, and ERC sign‑offs for TSMC advanced technology nodes (3nm/5nm/7nm).
• Collaborate with circuit designers to implement optimal layout topology for performance, power, and area (PPA).
• Optimize layout for matching, symmetry, and parasitic control.
• Run layout extraction (PEX) and assist with post‑layout simulation and debugging.
• Support timing, reliability (EM/IR), and yield enhancement reviews.
• Work closely with foundry teams to resolve DRC/DFM issues and implement layout‑friendly design methodologies.
• Maintain layout automation scripts and design checklists to improve team productivity.

Technical Skills:

• Process Nodes: Strong exposure to TSMC 3nm / 5nm / 7nm FinFET technologies.
• Tools: Cadence Virtuoso, Calibre, ICV, Synopsys Custom Compiler (or equivalent).
• Verification: DRC, LVS, PEX, DFM, antenna checks using Calibre/ Pegasus/ ICV.
• Scripting: Basic proficiency in SKILL, Tcl, or Python for automation.
• Memory Types: Experience in SRAM / ROM / CAM / Register File layout.
• Understanding of: Layout‑dependent effects (LDE), well proximity effects (WPE), and guard ring design.

Desired Profile:

• B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or related field.
• 3–10 years of hands‑on layout experience in advanced TSMC nodes.
• Strong layout debugging and problem‑solving skills.
• Ability to work effectively in a cross‑functional environment.
• Excellent communication and documentation skills.

Nice to Have:

• Experience with EDA automation/flow development.
• Familiarity with foundry tape‑out procedures.
• Prior work on high‑density or high‑speed memory products.
• Exposure to mixed‑signal or analog layout in FinFET nodes.