Senior Memory Design Engineer

LeadSoc Technologies Pvt Ltd; Hyderabad; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Hyderabad is seeking a Senior Memory Design Engineer to drive SRAM/memory IP development for advanced SoCs. You will lead memory architecture, transistor-level design, and silicon optimization across process nodes to deliver high-speed, low-power memories.

Responsibilities include designing and optimizing SRAM circuits, developing memory blocks, performing PVT simulations, post-layout verification, and collaborating with architecture, physical design, DFT, and

Qualifications

• 4–8 years of hands-on experience in SRAM or memory circuit design.
• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or related discipline.
• Proficiency with Cadence Virtuoso, Spectre, ADE XL/Assembler, and extraction tools such as Calibre xRC/StarRC.
• Experience with post-layout simulation, PEX, LVS/DRC, EM/IR, and silicon correlation.
• Scripting experience in Python, SKILL, Perl, or TCL is a plus.

Responsibilities

• Design and optimize SRAM and memory circuits for performance, power, area, and yield.
• Develop memory building blocks including bitcells, sense amplifiers, write drivers, row/column decoders, precharge circuits, redundancy, and peripheral logic.
• Perform transistor-level design, simulation, and verification across PVT corners, Monte Carlo, noise, and reliability analyses.
• Drive post-layout verification (PEX) and collaborate with layout teams for optimal matching and manufacturability.
• Support silicon bring-up, characterization, failure analysis, and yield improvement.
• Work closely with architecture, physical design, DFT, and product engineering teams throughout the memory development lifecycle.

Skills

CMOS device physics

Transistor-level design

Memory architecture

PVT analysis

Python scripting

Education

B.E./B.Tech/M.E./M.Tech in Electronics or related

Tools

Cadence Virtuoso

Cadence Spectre

ADE XL/Assembler

Calibre xRC/StarRC

Job description

Job Description

LeadSoc Technologies Pvt Ltd

Location

Hyderabad, Telangana, India

Work Mode

On-site

Industry

Semiconductor Manufacturing, IT Services and IT Consulting, Engineering Services

Senior Memory Design Engineer

Experience

4–8 Years

About The Role

Join a high-performance silicon engineering team developing next-generation SRAM and memory IP for advanced SoCs. You will drive memory architecture, circuit design, characterization, and silicon optimization to deliver high-speed, low-power, and robust memory solutions across leading-edge process technologies.

Key Responsibilities

• Design and optimize SRAM and memory circuits for performance, power, area, and yield.
• Develop memory building blocks including bitcells, sense amplifiers, write drivers, row/column decoders, precharge circuits, redundancy, and peripheral logic.
• Perform transistor-level design, simulation, and verification across PVT corners, Monte Carlo, noise, and reliability analyses.
• Drive post-layout verification (PEX) and collaborate with layout teams for optimal matching and manufacturability.
• Support silicon bring-up, characterization, failure analysis, and yield improvement.
• Work closely with architecture, physical design, DFT, and product engineering teams throughout the memory development lifecycle.

Required Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or related discipline.
• 4–8 years of hands-on experience in SRAM or memory circuit design.
• Strong understanding of CMOS device physics, transistor-level design, memory architecture, stability, and reliability.
• Proficiency with Cadence Virtuoso, Spectre, ADE XL/Assembler, and extraction tools such as Calibre xRC/StarRC.
• Experience with post-layout simulation, PEX, LVS/DRC, EM/IR, and silicon correlation.
• Scripting experience in Python, SKILL, Perl, or TCL is a plus.

Preferred Experience

• Experience with advanced process nodes (FinFET technologies).
• Exposure to high-performance CPU, GPU, AI Accelerator, Networking, or Data Center SoCs.
• Knowledge of low-voltage memory design, yield optimization, and low-power techniques.