Senior Memory Design Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking a Senior Memory Design Engineer to drive circuit-level design and optimization of memory macros, focusing on SRAM and advanced memory cells. You will work on bitcell, sense amplifiers, decoders, and peripheral circuits, performing schematic sizing, simulations, and PVT analysis.

The role requires 5-10 years in memory design, strong CAD skills, and collaboration with layout and silicon teams to ensure robust, high-yield memory solutions in a

Qualifications

• B.E./B.Tech./M.E./M.Tech in Electrical/Electronics/VLSI or related field.
• 5-10 years of experience in Memory Design or Custom Circuit Design.
• Strong background in SRAM / memory macro design and transistor-level techniques.

Responsibilities

• Design and optimize SRAM/Memory macros at transistor and circuit level.
• Develop bitcell, sense amplifier, precharge, write driver, decoders, and peripheral circuits.
• Perform schematic design, transistor sizing, simulations, and optimization.
• Analyze PVT, Monte Carlo, mismatch, variation, leakage, power, and performance.
• Drive memory timing, power, stability, and reliability characterization.
• Debug circuit-level issues and improve PPA and yield.
• Collaborate with Layout, STA, Verification, and Silicon teams for signoff.
• Support silicon correlation, characterization, and post-silicon debug.

Skills

SRAM / Memory circuit design

Transistor-level design

CMOS fundamentals

SPICE simulations

PVT analysis

Memory timing & yield optimization

Python/Perl/Tcl scripting

Education

B.E./B.Tech./M.E./M.Tech in Electrical/Electronics/VLSI or related

Tools

Cadence Virtuoso

Monte Carlo analysis tools

Job description

We are looking for a Senior Memory Design Engineer to drive circuit-level design and optimization of advanced memory macros. The role requires strong expertise in SRAM/Memory circuit design, custom transistor-level design, simulation, characterization, and PVT analysis.

Key Responsibilities

• Design and develop SRAM/Memory macros at transistor and circuit level.
• Work on bitcell, sense amplifier, precharge, write driver, decoder, and peripheral circuits.
• Perform schematic design, transistor sizing, simulations, and circuit optimization.
• Analyze PVT, Monte Carlo, mismatch, variation, leakage, power, and performance.
• Drive memory timing, power, stability, and reliability characterization.
• Debug circuit-level issues and improve PPA and yield.
• Collaborate with Layout, STA, Verification, and Silicon teams for memory macro development and signoff.
• Support silicon correlation, characterization, and post-silicon debug.

Core Technical Skills

• Strong hands-on experience in SRAM / Memory circuit design.
• Expertise in Cadence Virtuoso and transistor-level simulation.
• Strong understanding of CMOS fundamentals, device physics, and circuit analysis.
• Experience with SPICE simulations, PVT corners, Monte Carlo, and statistical analysis.
• Knowledge of memory timing, stability, leakage, power, and yield optimization.
• Exposure to advanced technology nodes and low-voltage memory design is a plus.
• Strong scripting/debugging skills using Python/Perl/Tcl is desirable.

Qualifications

• B.E./B.Tech/M.E./M.Tech in Electrical/Electronics/VLSI or related discipline.
• 5-10 years of relevant industry experience in Memory Design / Custom Circuit Design.