SRAM Memory Layout Engineer

Modernize Chip Solutions (MCS); Bengaluru; On-site; INR 1,200,000 - 1,600,000; Full time

Job summary

Modernize Chip Solutions (MCS) is seeking an experienced SRAM Memory Layout Engineer to drive memory macro layouts in Bangalore. The role covers layout development from floorplanning to tape-out with emphasis on area, timing, and reliability for advanced nodes.

The candidate should have hands-on experience in SRAM macros, access to Cadence Virtuoso and Calibre tools, and strong collaboration with Memory Design, Circuit Design, and Verification teams. 3–6 years of relevant experience is preferred.

Qualifications

• Experience in SRAM memory layout and related macro architectures.
• Strong debugging skills for physical verification and ECO handling.
• Ability to script layout automation using Tcl or Python.

Responsibilities

• Develop and optimize SRAM bit-cell arrays, sense amps, decoders, and periphery.
• Lead layout tasks across floorplanning, placement, routing, LVS/DRC checks and tape‑out.

Skills

SRAM layout

PV debugging

Scripting Tcl/Python

Tools

Cadence Virtuoso

Calibre DRC/LVS/PEX

Job description

SRAM Memory Layout Engineer

Experience: 3–6 Years

Location: Bangalore

Notice Period: Immediate to 60 Days

Technology: TSMC 2nm/3nm | Samsung 2nm/4nm

Job Description

We are looking for experienced SRAM Memory Layout Engineers with strong hands‑on expertise in advanced-node memory layout and physical verification. The ideal candidate should have experience working on SRAM macros and memory structures from layout development through tape‑out.

Key Responsibilities & Skills

• 3–6 years of hands‑on experience in SRAM Memory Layout.
• Strong experience with Single Port, Dual Port, Pseudo Dual Port SRAM, Register File, FIFO, and Embedded Memory macros.
• Hands‑on experience with TSMC 2nm/3nm and/or Samsung 2nm/4nm technology nodes.
• Develop and integrate bit‑cell arrays, sense amplifiers, decoders, column muxes, row/column periphery, and top‑level memory blocks.
• Experience across the complete layout lifecycle, including floorplanning, placement, routing, optimization, DRC/LVS/ERC, PEX, and tape‑out.
• Strong knowledge of matching, symmetry, EM/IR, density, antenna, ESD, and advanced‑node design rules.
• Proficiency in Cadence Virtuoso and Calibre DRC/LVS/PEX.
• Experience in area, performance, power, yield, and reliability optimization.
• Strong debugging skills with hands‑on experience in PV issue resolution and ECO implementation.
• Good scripting skills in Tcl/Python for layout automation and flow improvement will be an added advantage.
• Ability to collaborate effectively with Memory Design, Circuit Design, and Verification teams.

Preferred Candidate Profile

• Strong understanding of advanced-node SRAM layout methodologies.
• Good problem‑solving and debugging skills.
• Ability to independently handle layout tasks and resolve physical verification issues.
• Strong communication and cross‑functional collaboration skills.