Senior/Lead Physical Design Engineer-Bangalore & Hyderabad

MosChip®; Bengaluru; On-site; INR 4,200,000 - 5,600,000; Full time

Job summary

MosChip Technologies in Bengaluru is seeking a Senior/Lead Physical Design Engineer for on-site work in the Greater Bengaluru Area. The role focuses on leading physical design activities such as floorplanning, power planning, place-and-route, and timing closure for complex SoCs, while collaborating with RTL and circuit teams to ensure robust implementation.

The ideal candidate will have 4+ years in physical design, strong DV/verification experience, and a track record of successful tape-outs on

Qualifications

• Minimum 4 years of strong expertise in Physical Design including floorplanning, power planning, place-and-route, clock tree synthesis, and timing closure.
• Hands-on experience in Physical Verification, including DRC, LVS, EM/IR analysis, and sign-off methodologies.
• Solid background in Logic Design and RTL Design, with the ability to interpret specifications and collaborate with front-end teams.
• Knowledge of Circuit Design concepts, including understanding of standard cells, macros, I/O structures, and their impact on layout and timing.
• Proficiency with industry-standard EDA tools for physical design and verification (Cadence, Synopsys, or Siemens tools).
• Experience working on advanced process nodes and large, complex SoCs or ASICs, with prior involvement in successful tape-outs.
• Strong analytical, problem-solving, and debugging skills, with attention to detail and a focus on quality and schedule adherence.
• Ability to lead projects or sub-teams, mentor junior engineers, and communicate clearly with cross-functional stakeholders.
• Bachelor’s or Master’s degree in Electrical Engineering.

Responsibilities

• Lead and execute physical design activities including floorplanning, partitioning, power planning, place-and-route, clock tree synthesis, and timing closure for complex SoCs.
• Perform physical verification tasks such as DRC, LVS, EM/IR sign-off; collaborate with RTL, logic and circuit teams to ensure robust implementation.
• Analyze design constraints and optimize performance, power and area; drive design reviews.
• Mentor junior engineers and coordinate with cross-functional teams to meet tape-out schedules and quality targets.
• Contribute to methodology enhancements, automation scripts, and best practices for physical design and verification flows.

Skills

Physical Design

Floorplanning

Power planning

Place-and-route

Clock tree synthesis

Timing closure

Physical verification

DRC/LVS/EM/IR

Logic design

RTL design

Circuit design

EDA tools

Tape-outs

Project leadership

Communication

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Cadence

Synopsys

Siemens tools

Job description

MosChip® Technologies is a publicly traded company specializing in silicon and product engineering solutions, with a team of over 1300 engineers across Silicon Valley, USA, and India. The organization delivers end-to-end silicon design, verification, systems, software, and device engineering services, along with expertise in multimedia, mobility, connectivity, AI/ML solution design, and test automation. MosChip® also focuses on developing Digital IPs, Verification IPs, Mixed Signal IPs, and providing turnkey ASIC services. The company has shipped millions of connectivity ICs and holds a strong record of first-time-right silicon across more than 200 SoC tape-outs, offering engineers exposure to complex, high-impact semiconductor projects.

Role Description :

This is a full-time, on-site Senior/Lead Physical Design Engineer role located in the Greater Bengaluru Area, with opportunities to collaborate closely with teams in Hyderabad. The role involves leading and executing physical design activities including floorplanning, partitioning, power planning, place-and-route, clock tree synthesis, and timing closure for complex SoCs. The engineer will perform physical verification tasks such as DRC, LVS, and EM/IR sign-off, while working closely with RTL, logic, and circuit design teams to ensure robust implementation. Day-to-day responsibilities include analyzing design constraints, optimizing performance, power, and area, driving design reviews, mentoring junior engineers, and coordinating with cross-functional teams to achieve tape-out schedules and quality targets. The position may also involve contributing to methodology enhancements, automation scripts, and best practices for physical design and verification flows.

Qualifications:

• Minimum 4 Yrs of strong expertise in Physical Design, including floorplanning, power planning, place-and-route, clock tree synthesis, and timing closure.
• Hands‑on experience in Physical Verification, including DRC, LVS, EM/IR analysis, and sign-off methodologies.
• Solid background in Logic Design and RTL Design, with the ability to interpret specifications and collaborate effectively with front‑end teams.
• Knowledge of Circuit Design concepts, including understanding of standard cells, macros, I/O structures, and their impact on layout and timing.
• Proficiency with industry-standard EDA tools for physical design and verification (such as Cadence, Synopsys, or Siemens tools).
• Experience working on advanced process nodes and large, complex SoCs or ASICs, with prior involvement in successful tape-outs.
• Strong analytical, problem‑solving, and debugging skills, with attention to detail and a focus on quality and schedule adherence.
• Ability to lead projects or sub‑teams, mentor junior engineers, and communicate clearly with cross‑functional stakeholders.
• Bachelor’s or Master’s degree in Electrical Engineering,