STAFF Engineer -DEG Layout

1840 Micron Tech. OP India LLP; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP is seeking an experienced layout engineer to lead the design and development of critical analog and mixed-signal blocks. The role requires a minimum of 12 years of experience in analog design, proficiency in Cadence VLE/VXL and Mentor Graphics Calibre, and a strong understanding of layout fundamentals.

Ideal candidates will manage global engineering communications and deliver high-quality layouts on time. Exceptional verbal and written communication skills are crucial.

Qualifications

• 12 to 18 years of experience in analog/custom layout design within advanced CMOS processes.
• Proficiency in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Hands-on experience creating layouts for critical blocks such as PLL, ADC, DAC, etc.
• Strong understanding of analog layout fundamentals.
• Excellent problem-solving skills in physical verification of custom layouts.

Responsibilities

• Lead layout design and development of critical analog and digital blocks.
• Perform layout verification tasks such as LVS, DRC, and quality documentation.
• Develop digital block layouts using auto placement and routing tools.
• Guide and review sub-block level layouts of team members.
• Manage effective communication with global engineering teams.

Skills

Analog/custom layout design

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

AI tools

Physical verification

Job description

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.

Responsibilities

• Lead layout design and development of critical analog, mixed‑signal, custom digital blocks, standard cells, and full chip level.
• Perform layout verification tasks such as LVS, DRC, antenna, shield, matching, latch‑up, EM, IR totem checks, and quality documentation.
• Develop digital block layouts using auto placement and routing tools.
• Maintain a basic understanding of skill coding and automation for layout processes.
• Deliver block‑level layouts on time while ensuring acceptable quality.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project milestones across multiple projects.
• Guide and review sub‑block level layouts of team members.
• Manage effective communication with global engineering teams to assure layout project success.
• Reduce layout effort through the use of AI tools.

Qualifications and Requirements

• 12 to 18 years of experience in analog/custom layout design within advanced CMOS processes.
• Proficiency in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Hands‑on experience creating layouts for critical blocks such as temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparator, differential amplifier, etc.
• Strong understanding of analog layout fundamentals, including matching, electro‑migration, latch‑up, coupling, crosstalk, IR‑drop, and parasitic effects.
• Capability to assess layout impact on circuit performance, speed, capacitance, power, and area.
• Ability to understand design constraints and implement high‑quality layouts.
• Excellent command of and problem‑solving skills in physical verification of custom layouts.
• Experience with tape‑out support is an added advantage.
• Skill in automating layout execution tasks using AI tools.
• Excellent verbal and written communication skills.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Micron prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.