Senior DFT Engineer

Swediumglobal; Bengaluru; On-site; INR 1,000,000 - 2,000,000; Full time

Job summary

A growing System Engineering and Solution Company in Bengaluru is seeking a DFT Engineer to join its ASIC design team. This role involves developing design-for-test methodologies, including scan insertion and ATPG pattern generation for complex SoCs. The ideal candidate will have over 7 years of DFT implementation experience, a degree in Electrical Engineering or a related field, and strong analytical and problem-solving skills. The position is onsite, with a collaborative environment focused on quality testable silicon.

Qualifications

• 7+ years of hands-on experience in ASIC/SoC DFT implementation.
• Strong understanding of scan insertion and scan architecture.
• Proficiency in DFT EDA tools.

Responsibilities

• Develop and implement DFT architecture for ASIC/SoC designs.
• Insert and verify scan chains, boundary scan (JTAG), MBIST, and LBIST structures.
• Perform ATPG pattern generation for various faults.

Skills

Scan insertion and scan architecture

ATPG (stuck-at, transition faults)

MBIST/LBIST methodologies

Boundary scan (IEEE 1149.1)

Problem-solving

Analytical skills

Communication skills

Education

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field

Tools

Synopsys DFT Compiler

TetraMAX / TestMAX

Cadence Modus

Job description

Overview

Swedium Global is the growing System Engineering and Solution Company, offering services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to clients across the globe for an onsite and offshore business model. Swedium Global has presence in Sweden, Finland, Poland, Czech Republic and in India.

Experience-7+ Years

Location- Onsite in Bangalore -5 Days of office

Job Name: DFT Engineer-ASIC

Job Summary

We are seeking a DFT Engineer to join our ASIC design team to develop and implement design-for-test methodologies for complex SoCs. The DFT engineer will be responsible for scan insertion, BIST implementation, ATPG pattern generation, and test coverage analysis to ensure high-quality, testable silicon.

Key Responsibilities

• Develop and implement DFT architecture for ASIC/SoC designs in collaboration with front-end and back-end design teams.
• Insert and verify scan chains, boundary scan (JTAG), MBIST, and LBIST structures at RTL or gate level.
• Perform ATPG pattern generation for stuck-at, transition, and path delay faults; analyze and improve test coverage.
• Plan and integrate test compression and diagnostic features to reduce test time and cost.
• Ensure DFT rule compliance throughout the synthesis and implementation flow.
• Collaborate with the physical design team for DFT constraint setup, timing closure, and test mode verification.
• Support silicon bring-up, pattern validation, and failure debug during post-silicon testing.
• Maintain DFT scripts and automation for improved efficiency and consistency across projects.
• Work with ATE (Automated Test Equipment) engineers to ensure smooth pattern transfer and test execution.
• Document DFT methodologies, coverage metrics, and sign-off reports.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
• 7+ years of hands-on experience in ASIC/SoC DFT implementation.
• Strong understanding of:
• Scan insertion and scan architecture
• ATPG (stuck-at, transition faults)
• MBIST/LBIST methodologies
• Boundary scan (IEEE 1149.1)
• Proficiency in DFT EDA tools, such as:
• Synopsys DFT Compiler, TetraMAX / TestMAX
• Cadence Modus
• Solid understanding of ASIC design flow— synthesis, timing, verification, and P&R.
• Working knowledge of Verilog/SystemVerilog and scripting languages (TCL, Perl, Python, or Shell).
• Familiarity with ATE testing concepts and pattern debug.
• Excellent problem-solving, analytical, and communication skills.