Senior/Lead DFT engineer : Noida/Hyderabad

Incise Infotech; Hyderabad, Dadri; On-site; INR 4,000,000 - 9,000,000; Full time

Job summary

Incise Infotech is seeking an experienced DFT Engineer with 7+ years of expertise in ASIC/SoC DFT implementation and verification. You will lead design-for-test architecture, drive scan insertion, ATPG, MBIST/LBIST, and JTAG readiness while coordinating with RTL and physical design teams.

Ideal candidates will have hands-on Verilog/SystemVerilog, strong problem-solving abilities, and a track record of reducing test time and costs in complex silicon projects. On-site opportunity in Hyderabad.

Qualifications

• 7+ years of experience in DFT implementation for ASIC/SoC designs.
• Strong knowledge of Scan, Scan Compression, ATPG, MBIST, LBIST, and JTAG.
• Hands-on experience with Verilog/SystemVerilog.
• Good understanding of RTL design flow and digital design fundamentals.
• Familiarity with synthesis, STA and physical design constraints related to DFT.
• Experience debugging DFT issues and improving test coverage.
• Strong analytical, problem-solving, and communication skills.

Responsibilities

• Develop and implement DFT architecture for complex ASIC/SoC designs.
• Perform scan insertion, scan compression, and ATPG pattern generation.
• Implement and verify MBIST, LBIST, and JTAG per IEEE 1149.1.
• Analyze and improve test coverage while reducing test time and cost.
• Collaborate with RTL, Physical Design, Verification, and Test teams throughout the design cycle.
• Debug DFT-related issues during simulation, synthesis, and silicon bring-up.
• Support post-silicon validation and production testing.

Skills

DFT expertise

ATPG

MBIST/LBIST

JTAG

Verilog/SystemVerilog

RTL design flow

Scripting: Tcl/Perl/Python

Communication skills

ASIC/SoC design

Debugging DFT

Tools

Tessent

Synopsys DFT Compiler

TestMAX

Job description

Job Description

We are looking for an experienced DFT (Design for Test) Engineer with 7+ years of expertise in ASIC/SoC Design‑for‑Test implementation and verification. The ideal candidate should have hands‑on experience in DFT architecture, scan insertion, ATPG, MBIST, and JTAG, along with strong knowledge of industry‑standard EDA tools.

Key Responsibilities

• Develop and implement DFT architecture for complex ASIC/SoC designs.
• Perform scan insertion, scan compression, and ATPG pattern generation.
• Implement and verify MBIST, LBIST, JTAG (IEEE 1149.1), and boundary scan.
• Analyze and improve test coverage while reducing test time and test cost.
• Work closely with RTL, Physical Design, Verification, and Test teams throughout the design cycle.
• Debug DFT‑related issues during simulation, synthesis, and silicon bring‑up.
• Support post‑silicon validation and production testing.

Required Skills

• 7+ years of experience in DFT implementation for ASIC/SoC designs.
• Strong knowledge of Scan, Scan Compression, ATPG, MBIST, LBIST, and JTAG.
• Experience with Tessent, Synopsys DFT Compiler, TestMAX, or equivalent DFT tools.
• Hands‑on experience with Verilog/SystemVerilog.
• Good understanding of digital design fundamentals and RTL design flow.
• Familiarity with synthesis, STA, and physical design constraints related to DFT.
• Experience debugging DFT issues and improving test coverage.
• Strong analytical, problem‑solving, and communication skills.

Preferred Skills

• Experience with advanced technology nodes (16nm/7nm/5nm and below).
• Knowledge of IEEE 1500, IEEE 1687 (IJTAG), and advanced DFT methodologies.
• Exposure to Automotive, AI/ML, Networking, or High‑Performance Computing SoCs.
• Experience with scripting languages such as Tcl, Perl, or Python.